DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 17

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
3.
4.
Clock-to-Output Times
Setup Times
Hold Times
T
Symbol
T
T
The numbers in this table are tested using the methodology presented in
Table 8
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
The numbers in this table are tested using the methodology presented in
Table 8
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
T
T
Symbol
ICKOFDCM
PSDCM
PHDCM
T
PSFD
PHFD
ICKOF
and
and
R
Table
Table
When writing to the Input Flip-Flop (IFF), the
time from the setup of data at the Input pin to
the active transition at a Global Clock pin. The
DCM is in use. No Input Delay is programmed.
When writing to IFF, the time from the setup of
data at the Input pin to an active transition at
the Global Clock pin. The DCM is not in use.
The Input Delay is programmed.
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is in use. No Input Delay is programmed.
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is not in use. The Input Delay is
programmed.
When reading from the Output Flip-Flop
(OFF), the time from the active transition
on the Global Clock pin to data appearing
at the Output pin. The DCM is in use.
When reading from OFF, the time from
the active transition on the Global Clock
pin to data appearing at the Output pin.
The DCM is not in use.
11.
11.
Table
23. If the latter is true, add the appropriate Output adjustment from
Description
Description
www.xilinx.com
LVCMOS25
output drive, Fast slew rate,
with DCM
LVCMOS25
output drive, Fast slew rate,
without DCM
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 6,
without DCM
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 6,
without DCM
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Conditions
(3)
Conditions
Table 27
Table 27
(2)
(2)
(4)
(4)
, 12 mA
, 12 mA
(2)
(2)
(3)
(3)
,
,
,
,
and are based on the operating conditions set forth in
and are based on the operating conditions set forth in
Table
Table
XA3SD1800A
XA3SD3400A
XA3SD1800A
XA3SD3400A
23. If this is true of the data Input, subtract the
23. If this is true of the data Input, add the
XA3SD1800A
XA3SD3400A
XA3SD1800A
XA3SD3400A
XA3SD1800A
XA3SD3400A
XA3SD1800A
XA3SD3400A
Table
Device
Device
26.
Speed Grade
Speed Grade
Max
3.51
3.82
5.58
6.13
-4
-0.38
-0.26
-0.71
-0.65
3.11
2.49
3.39
3.08
Min
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17