DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 40

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Digital Frequency Synthesizer
Table 39: Recommended Operating Conditions for the DFS
Table 40: Switching Characteristics for the DFS
Notes:
1.
2.
3.
4.
5.
6.
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
3.
4.
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter
CLKOUT_PER_JITT_FX
Duty Cycle
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
Phase Alignment
CLKOUT_PHASE_FX
CLKOUT_PHASE_FX180
Lock Time
LOCK_FX
Input Frequency Ranges
F
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
CLKIN
The numbers in this table are based on the operating conditions set forth in
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an FPGA. Output jitter strongly
depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency,
power supply and PCB design. The actual maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum
CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
(2,3)
Symbol
(5,6)
CLKIN_FREQ_FX
Symbol
R
(6)
(3,4)
(2)
(2)
Frequency for the CLKFX and CLKFX180 outputs
Period jitter at the CLKFX and CLKFX180
outputs.
including the BUFGMUX and clock tree duty-cycle distortion
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals are
valid. If using both the DLL and the DFS, use
the longer locking time.
(3)
Frequency for the CLKIN input
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency
Period jitter at the CLKIN input
Description
www.xilinx.com
Description
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
F
5 MHz < F
CLKIN
≤
> 20 MHz
< 15 MHz
Table 8
CLKIN
CLKIN
20 MHz
> 15 MHz
CLKIN
and
Table
F
F
Device
CLKFX
CLKFX
All
All
All
All
All
All
39.
< 150 MHz
> 150 MHz
www.xilinx.com/support/documentation/
±[1% of CLKFX
period + 100]
Use the Spartan-3A FPGA Jitter
data_sheets/s3a_jitter_calc.zip
Min
Typ
5
-
-
-
-
-
Speed Grade
Calculator:
-4
Speed Grade
Min
0.2
-
-
-
±[1% of CLKFX
±[1% of CLKFX
±[1% of CLKFX
period + 200]
period + 350]
period + 200]
-4
±200
Max
Max
311
450
±300
±150
Table
5
Max
333
±1
37.
Units
MHz
ps
ps
ns
Units
MHz
ms
ps
ps
ps
ps
ps
μs
40