DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 19

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Table 21: Sample Window (Source Synchronous)
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
3.
T
Set/Reset Pulse Width
T
Symbol
T
Symbol
IOICKPD
RPW_IOB
SAMP
The numbers in this table are tested using the methodology presented in
Table 8
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
Setup and hold
capture window of
an IOB flip-flop
and
Time from the active transition at the ICLK input
of the Input Flip-Flop (IFF) to the point where
data must be held at the Input pin. The Input
Delay is programmed.
Minimum pulse width to SR control input on
IOB
R
Description
Table
11.
Description
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record
Table
Table
23.
23. When the hold time is negative, it is possible to change the data before the clock’s active
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LVCMOS25
-
Conditions
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
(2)
Table 27
Max
IFD_DELAY_
VALUE
and are based on the operating conditions set forth in
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
-
XA3SD1800A
XA3SD3400A
Device
All
Speed Grade
-1.40
-2.11
-2.48
-2.77
-2.62
-3.06
-3.42
-3.65
-1.31
-1.88
-2.44
-2.89
-2.83
-3.33
-3.63
-3.96
1.61
Min
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
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