ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 39

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ssd1908

Manufacturer Part Number
ssd1908
Description
Lcd Drivers,lcd Controllers
Manufacturer
Solomon Systech Limited:
Datasheet
REG[23h] bits 1-0,
REG[22h] bits 7-0
Bit 7
Bits 2-0
Reset
Reset
Reset
Type
state
Type
state
Type
state
SSD1908
Bit
Bit
Bit
LLINE Pulse Start Position Register 0
LLINE Pulse Start Position Register 1
LFRAME Pulse Width Register
Position Bit
Pulse Start
LFRAME
Polarity
LLINE
Pulse
RW
RW
NA
7
7
0
7
0
0
7
0
Rev 1.0
Position Bit
Pulse Start
LLINE
LLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in number of PCLK.
LLINE Pulses Start Position in PCLK = Bits [9:0] + 1
Note
For panel AC timing and timing parameter definitions, see Section10.4 “Display Interface”.
LFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. The vertical sync signal is
typically named as LFRAME or SPS or VSD, depending on the panel type.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
LFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The
vertical sync signal is typically named as LFRAME or SPS or VSD, depending on the
panel type.
LFRAME Pulse Width in number of pixels = (Bits [2:0] + 1) x Horizontal Total + offset
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display Interface”.
RW
NA
NA
6
6
0
6
0
0
6
0
0
P 29/29
Position Bit
Pulse Start
Oct 2003
LLINE
RW
NA
NA
5
5
0
5
0
0
5
0
0
Position Bit
Pulse Start
LLINE
RW
NA
NA
4
4
0
4
0
0
4
0
0
Position Bit
Pulse Start
LLINE
RW
NA
NA
3
3
0
3
0
0
3
0
0
Pulse Width
Position Bit
Pulse Start
LFRAME
LLINE
Bit 2
RW
RW
NA
2
2
0
2
0
0
2
0
Pulse Width
Position Bit
Position Bit
Pulse Start
Pulse Start
Solomon Systech
LFRAME
LLINE
LLINE
Bit 1
RW
RW
RW
1
1
0
1
9
0
1
0
REG[22h]
REG[23h]
REG[24h]
Pulse Width
Position Bit
Position Bit
Pulse Start
Pulse Start
LFRAME
LLINE
LLINE
Bit 0
RW
RW
RW
0
0
0
0
8
0
0
0

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