ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 83

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

1. t
SSD1908
11
is the delay from when data is placed on the bus until the data is latched into the write buffer.
Symbol
T
f
BUSCLK
BUSCLK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
7a
7b
7d
10
11
12
13
14
15
7c
1
2
3
4
5
6
8
9
Rev 1.0
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
SA[17:0], M/R#, SBHE# setup to first BUSCLK rising edge
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[17:0], M/R#, SBHE# hold from either MEMR# or MEMW#
rising edge
CS# setup to BUSCLK rising edge
CS# hold from either MEMR# or MEMW# rising edge
MEMR# or MEMW# asserted for MCLK = BCLK
MEMR# or MEMW# asserted for MCLK = BCLK ÷2
MEMR# or MEMW# asserted for MCLK = BCLK ÷3
MEMR# or MEMW# asserted for MCLK = BCLK ÷4
MEMR# or MEMW# setup to BUSCLK rising edge
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
MEMW#=0 (write cycle)(see note1)
SD[15:0] hold from IOCHRDY rising edge (write cycle)
MEMR# falling edge to SD[15:0] driven (read cycle)
IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
cycle)
P 73/73
Table 10-5 : Generic #2 Interface Timing
Oct 2003
Parameter
1/f
BUSCLK
Min
6
6
1
0
1
0
1
3
3
0
0
3
3
Solomon Systech
Max
66
13
18
23
28
15
13
13
12
2
T
T
T
T
Units
BUSCLK
MHz
BUSCLK
BUSCLK
BUSCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns