ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 41

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

REG[35h] bits 1-0
REG[34h] bits 7-0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reset
Reset
Reset
Type
state
Type
state
Type
state
SSD1908
Bit
Bit
Bit
LFRAME Pulse Stop Offset Register 0
LFRAME Pulse Stop Offset Register 1
HR-TFT Special Output Register
Stop Offset
LFRAME
Enable
Preset
LDEN
Bit 7
RW
RW
NA
7
0
7
0
0
7
0
Rev 1.0
Stop Offset
LFRAME
Control
GPIO1
LFRAME Pulse Stop Offset [9:0]
These bits specify the stop offset of the vertical sync signal within a line, in 1 pixel
resolution.
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display Interface”.
LDEN Preset Enable
When this bit = 1, LDEN signal should be programmed with the appropriate values with
REG[3Ch], [3Eh].
When this bit = 0, LDEN signal are preset to defined values.
GPIO1 Control
When this bit = 1, GPIO1 should be programmed with the appropriate values with
REG[3Ah] and [3Bh].
When this bit = 0, GPIO1 can be toggle once per line.
GPIO Preset Enable
When this bit = 1, GPIO0 should be programmed with the appropriate values with
REG[3Ch], [3Eh]; GPIO1 can be controlled by REG[38h] bit 6 and GPIO2 should be
programmed with REG[40h].
When this bit = 0, GPIO0, GPIO1 and GPIO2 signals are preset to defined values.
LSHIFT Polarity Swap
When this bit = 1, LSHIFT signal is falling trigger.
When this bit = 0, LSHIFT signal is rising trigger.
LSHIFT Mask
When this bit = 1, LSHIFT signal is enabled in non display period.
When this bit = 0, LSHIFT signal is masked in non display period.
GPIO0 / GPIO1 Swap
When this bit = 1, GPIO0 / GPIO1 signals are swapped.
When this bit = 0, GPIO0 / GPIO1 signals are not swapped.
Bit 6
RW
RW
NA
6
0
6
0
0
6
0
P 31/31
Stop Offset
LFRAME
Oct 2003
Enable
Preset
GPIO
Bit 5
RW
RW
NA
5
0
5
0
0
5
0
Stop Offset
LFRAME
LSHIFT
Polarity
swap
Bit 4
RW
RW
NA
4
0
4
0
0
4
0
Stop Offset
LFRAME
LSHIFT
Mask
Bit 3
RW
RW
NA
3
0
3
0
0
3
0
Stop Offset
LFRAME
GPIO0 /
GPIO1
Swap
Bit 2
RW
RW
NA
2
0
2
0
0
2
0
Stop Offset
Stop Offset
Solomon Systech
LFRAME
LFRAME
Alternate
Bit 1
Bit 9
RW
RW
RW
PS
1
0
0
1
0
1
REG[34h]
REG[35h]
REG[38h]
CLS Double
Stop Offset
Stop Offset
LFRAME
LFRAME
Bit 0
Bit 8
RW
RW
RW
0
0
0
0
0
0