ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 45

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

Bits 7-6
Bits 5-3
Bits 2-0
Reset
Type
state
SSD1908
Bit
Analog TFT Control Register
Reserved
* For REG[22] = 0,
START1 = 0 Ts if REG[3Ah] = 00; STOP1 = n+1 Ts if REG[3Bh] = n
START0 = 0 Ts if REG[3Ch] = 00; STOP0 = n+1 Ts if REG[3Eh] = n
DELAY = 0 Ts if REG[40h] = 00
GPIO2
LLINE
GPIO1
GPIO0
(REV)
(CLS)
RW
(LP)
(PS)
7
0
Rev 1.0
Reserved
For panel AC timing and timing parameter definitions, see Section 10.4.9 “Generic HR-
TFT Panel Timing ”.
Reserved bits
These bits should be programmed by 0.
Even line RGB sequence bits [2:0]
These bits specify the output sequence of the RGB elements for even lines in Analog
TFT mode. See Table 7-7 : RGB Sequence Selection.
Odd line RGB sequence bits [2:0]
These bits specify the output sequence of the RGB elements for odd lines in Analog
TFT mode. See Table 7-7 : RGB Sequence Selection.
Note
This register is effective for Analog TFT only (REG[10h] bits 2:0 = 100).
RW
6
0
P 35/35
DELAY
START1
START0
Figure 7-2 : GPIO offset for 320x240 HR-TFT
sequence
Even line
Oct 2003
RGB
Bit 2
RW
5
0
sequence
Even line
RGB
Bit 1
RW
4
0
STOP1
STOP0
sequence
Even line
RGB
Bit 0
RW
3
0
sequence
Odd line
RGB
Bit 2
RW
2
0
Solomon Systech
sequence
Odd line
RGB
Bit 1
RW
1
0
REG[42h]
sequence
Odd line
RGB
Bit 0
RW
0
0