ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 85

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

1. t
SSD1908
17
is the delay from when data is placed on the bus until the data is latched into the write buffer.
Symbol
T
f
CLK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
t
t
t
t
t
t
t
t
7a
7b
7d
10
11
12
13
14
15
16
17
18
19
20
21
7c
1
2
3
4
5
6
8
9
Rev 1.0
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[17:1], M/R# setup to first CLK rising edge where CS# = 0,
AS#=0,UDS#=0,and LDS#=0
A[17:1], M/R# hold from AS# rising edge
CS# setup to CLK rising edge while AS#, UDS#/LDS# = 0
CS# hold from AS# rising edge
AS# asserted for MCLK = BCLK
AS# asserted for MCLK = BCLK ÷2
AS# asserted for MCLK = BCLK ÷3
AS# asserted for MCLK = BCLK ÷4
AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# =0
AS# setup to CLK rising edge
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
UDS#/LDS# = 0
UDS#/LDS# high setup to CLK rising edge
First CLK rising edge where AS#=1 to DTACK# high
impedance
R/W# setup to CLK rising edge before all CS#, AS#, UDS#
and/or LDS# = 0
R/W# hold from AS# rising edge
AS# = 0 and CS# = 0 to DTACK# driven high
AS# rising edge to DTACK# rising edge
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0
and either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
D[15:0] hold from DTACK# falling edge (write cycle)
UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle)
DTACK# falling edge to D[15:0] valid (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance (read
cycle)
P 75/75
Table 10-6 : Motorola MC68K #1 Interface Timing
Oct 2003
Parameter
1/f
Min
6
6
1
0
1
0
1
2
1
2
3
1
0
3
4
0
0
3
3
CLK
Solomon Systech
Max
66
13
18
23
28
14
13
16
13
13
2
Units
MHz
T
T
T
T
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
CLK