h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 264

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h8s-2111b

Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
11.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 11.5.
11.5
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 11.2 WDT Interrupt Source
Rev. 1.00, 05/04, page 230 of 544
Name
WOVI
Overflow signal
(internal signal)
φ
OVF
RESO signal
Internal reset
signal
TCNT
RESO Signal Output Timing
Interrupt Sources
Interrupt Source
TCNT overflow
Figure 11.5 Output Timing of RESO signal
H'FF
Interrupt Flag
OVF
132 states
518 states
H'00

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