h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 371

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

13.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal
Table 13.8 I
Note:
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
ICDRS)
ICDRR)
*
Usage Notes
6t
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12t
2
cyc
C bus interface AC timing specifications will not be met with a
when 1.
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
cyc
, as shown in section 22, Electrical
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– (6t
to 256t
– 3t
– 1t
– 1t
+ 2t
cyc
cyc
Rev. 1.00, 05/04, page 337 of 544
cyc
cyc
cyc
or 12t
cyc
cyc
*)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
C bus output
C bus, neither
Notes
See figure
22.22.