h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 401
h8s-2111b
Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2111B.pdf
(582 pages)
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This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC
module supports only I/O read cycle and I/O write cycle transfers.
It is also provided with power-down functions that can control the PCI clock and shut down the
host interface.
15.1
• Supports LPC interface I/O read cycles and I/O write cycles
• Has three register sets comprising data and status registers
• Supports SERIRQ
• Eleven interrupt sources
IFHSTL0A_020020040200
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively. A fast
The I/O address can be set for channel 3. Sixteen bidirectional data register bytes can be
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
and status register (STR).
A20 gate function is also provided.
manipulated in addition to the basic register set.
Features
Section 15 Host Interface (LPC)
Rev. 1.00, 05/04, page 367 of 544
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