h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 420

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

• STR3 (TWRE = 0 and SELSTR3 = 1)
Note:
Rev. 1.00, 05/04, page 386 of 544
Bit
7
6
5
4
3
2
1
0
*
Bit Name
DBU37
DBU36
DBU35
DBU34
C/D3
DBU32
IBF3A
OBF3A
Only 0 can be written to clear the flag.
Initial
Value Slave
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R
R/(W)* R
R/W
Host Description
R
R
R
R
R
R
R
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor (this
LSI). IBF is cleared to 0 when the slave processor reads
IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
1: [Setting condition]
Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host processor
reads ODR.
0: [Clearing condition]
1: [Setting condition]
When the slave processor reads IDR
When the host processor writes to IDR using I/O
write cycle
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
When the slave processor writes to ODR