h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 432

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h8s-2111b

Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3.
15.4.3
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
Rev. 1.00, 05/04, page 398 of 544
LCLK
LFRAME
LAD3–LAD0
Number of clocks
LCLK
LFRAME
LAD3–LAD0
A20 Gate
1
Start
Start
Cycle type,
direction,
and size
Cycle type,
direction,
and size
Figure 15.2 Typical LFRAME Timing
1
Figure 15.3 Abort Mechanism
ADDR
ADDR
4
TAR
TAR
Too many Syncs
cause timeout
2
Sync
Sync
Slave must stop driving
1
Data
2
TAR
2
Start
Master will
drive high
1

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