h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 365
h8s-2111b
Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2111B.pdf
(582 pages)
- Current page: 365 of 582
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13.4.7
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
IRIC Setting Timing and SCL Control
7
7
7
7
Figure 13.25 IRIC Setting Timing and SCL Control (1)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
8
8
8
8
2
C bus format, no wait)
9
A
9
A
Clear IRIC
Clear IRIC
1
1
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00, 05/04, page 331 of 544
2
2
3
1
1
3
Clear IRIC
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