HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 7

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

The rounding algorithm is as follows:
The output of the rounder is latched into the HDF output
register with CK_DEC. CK_DEC is generated by the Clock
Divider section. The output of the register is cleared when
RESET is asserted.
DDF Control Registers
F_Register (A1 = 0, A0 = 0)
Fractional Portion Greater Than or Equal to 0.5
Fractional Portion Less Than 0.5
Fractional Portion Less Than or Equal to 0.5
Fractional Portion Greater Than 0.5
F_OAD
15
FA0
NEGATIVE NUMBERS
POSITIVE NUMBERS
F_BYP
14
FB0
F_ESYM
13
ES0
3-200
12
D3 D2 D1 D0 T8 T7 T6 T5 T4 T3 T2 T1 T0
11
F_DRATE
10
9
Round Up
Round Up
Truncate
Truncate
8
7
F_TAPS
Bits T0-T8 are used to specify the number of FIR filter taps. The number
entered is one less than the number of taps required. For example, to
specify a 511 tap filter F_TAPS would be programmed to 510. The mini-
mum number of FIR taps = 3 (F_TAPS = 2).
F_DRATE
Bits D0-D3 are used to specify the amount of FIR decimation. The num-
ber entered is one less than the decimation required. For example, to
specify decimation of 16, F_DRATE would be programmed to 15. For no
FIR decimation, F_DRATE would be set equal to 0. FDRATE +1 is
defined as F
F_ESYM
Bit ES0 is used to select the FIR symmetry. F_ESYM is set equal to one
to select even symmetry and set equal to zero to select odd symmetry.
When F_ESYM is one, data is added in the pre-adder; when it is zero,
data is subtracted. Normally set to one.
F_BYP
FB0 is used to select FIR bypass mode. FIR bypass mode is selected by
setting F_BYP = 1. When FIR bypass mode is selected, the FIR is inter-
nally set up for a 3 tap even symmetric filter, no decimation (F_DRATE =
0) and F_OAD is set equal to one to zero one side of the preadder. In FIR
bypass mode all FIR filter parameters, except F_CLA, are ignored, includ-
ing the contents of the FIR coefficient RAM. In FIR bypass mode the out-
put data is brought output on the lower 16 bits of the output bus
DATA_OUT 0-15. To disable FIR bypass mode, F_BYP is set equal to
zero. When F_BYP is returned to zero, the coefficients must be reloaded.
F_OAD
Bit FA0 is used to select the zero the preadder mode. This mode zeros
one of the inputs to the pre-adder. Zero preadder mode is selected by
setting F_OAD equal to one. This feature is useful when implementing
arbitrary phase filters or can be used to verify the filter coefficients. To
disable the Zero Preadder mode F_OAD is set equal to zero.
HSP43220
6
FIGURE 4.
5
F_TAPS
4
Clock Divider and Control Logic
The clock divider divides CK_IN by the decimation factor
H
Register, Comb Filter section, HDF output register. In the
FIR filter CK_DEC is used to indicate that a new data
sample is available for processing. The clock generator is
cleared by RESET and is not enabled until the DDF is
started by an internal start signal (see Start Logic).
The Control Register Logic enables the updating of the Control
registers which contain all of the filter parameter data. When
WR and CS are asserted, the control register addressed by bits
A0 and A1 is loaded with the data on the C_BUS.
DEC
DEC
3
.
to produce CK_DEC. CK_DEC clocks the Decimation
2
1
0