HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 4

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

Pinouts
Pin Description
DATA_IN0-15
C_BUS0-15
DATA_OUT
DATA_RDY
FIR_CK
RESET
NAME
CK_IN
GND
V
0-23
WR
CS
CC
(Continued)
TYPE
O
O
I
I
I
I
I
I
I
The +5V power supply pins.
The device ground.
Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro-
nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit
15 is the MSB.
Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select
the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0
and A1
Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of
the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the
FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not by-
passed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode.
An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle
is available on the data bus.
RESET is an asynchronous signal which requires that the input clocks CK_IN and FIR_CK are active when RESET is as-
serted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path is
not initialized. The control register bits that are cleared are F_BYP, H_STAGES, and H_DRATE. The F_DIS bit is set. In order
to guarantee consistent operation of the part, the user must reset the DDF after power up.
Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of
WR will latch the C_BUS0-15 data into the register specified by A0 and A1.
Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address
lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate
register as specified by A0 and A1.
STARTOUT
3-197
ASTARTIN
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
STARTIN
C_BUS 9
C_BUS 8
C_BUS 7
C_BUS 6
RESET
GND
V
V
WR
CS
CC
A1
A0
CC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
84 PLASTIC LEADED CHIP CARRIER (PLCC)
HSP43220
DESCRIPTION
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
V
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
CC