HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 11

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

There are two multiplexers that route 24 of the 40 output bits
from the output register to the output pins. The first
multiplexer selects the output register bits that will be routed
to output pins DATA_OUT16-23 and the second multiplexer
selects the output register bits that will be routed to output
pins DATA_OUT0-15.
The multiplexers are controlled by the control signal F_BYP
and the OUT_SELH pin. F_BYP and OUT_SELH both
control the first multiplexer that selects the upper 8 bits of
the output bus, DATA_OUT16-23. F_BYP controls the
second multiplexer that selects the lower 16 bits of the
F_DRATE
FROM COEFFICIENT
FIR_CK
FROM CONTROL REGISTERS
OUT_SELH
F_TAPS
FORMATTER
FIR CONTROL LOGIC
FROM HDF
F_BYP
OUT_ENX
OUT_SELH = 1
DATA_RDY
3-204
F_BYP = 0
REG
2
8
- 2
F_BYP
DATA_OUT16-23
20
16
1
8
MUX
8
8
COEFFICIENT
16 x 512
20 x 256
FIGURE 10. FIR OUTPUT FORMATTER
F_DIS
2
F_BYP = 0
DATA
OUT_SELH = 0
RAM
RAM
-16
F_BYP = 1
- 2
OR
-23
FIGURE 9. FIR FILTER
HSP43220
MULTIPLIER/
ACCUMULATOR
SECTION
DATA_RDY
16
16
20
FIR_CK
40
output bus, DATA_OUT0-15. The output formatter is shown
in detail in Figure 10.
FIR Control Logic
The DATA_RDY strobe indicates that new data is available on
the output of the FIR. The rising edge of DATA_RDY can be
used to load the output data into an external register or RAM.
Data Format
The DDF maintains 16 bits of accuracy in both the HDF and
FIR filter stages. The data formats and bit weightings are
shown in Figure 11.
F_CLA
F_OAD
F_CLA
F_BYP = 0
MUX
2
0
- 2
REG
REG
17 x 20 BIT MULTIPLIER ARRAY
-15
REG
DATA_OUT0 -15
20
43-BIT ACCUMULATOR
16 16
PRE-ADDER LOGIC
DATA_OUT 0 -23
MUX
16
16
OUTPUT REG
FORMATTER
16
OUTPUT
REG
37
37
PRE-ADDER
2
F_BYP = 1
43
40
24
-16
F_ESYM
- 2
OUT_ENP
-31
REG
F_BYP
17
17
17
43
REG