HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 12

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

FOR: OUT_SELH = 1, F_BYP = 0
FOR: OUT_SELH = 0, F_BYP = 0
FOR: OUT_SELH = X, F_BYP = 1
Operational Section
Start Configurations
The scenario to put the DDF into operational mode is: reset
the DDF by asserting the RESET input, configure the DDF
over the control bus, and apply a start signal, either by
ASTARTIN or STARTIN. Until the DDF is put in operational
mode with a start pulse, the DDF ignores all data inputs.
To use the asynchronous start, an asynchronous active low
pulse is applied to the ASTARTIN input. ASTARTIN is
internally synchronized to the sample clock, CK_IN, and
generates STARTOUT. This signal is also used internally
when the asynchronous mode is selected. It puts the DDF in
operational mode and allows the DDF to begin accepting
data. When the ASTARTIN input is being used, the STARTIN
input must be tied high to ensure proper operation.
To start the DDF synchronously, the STARTIN is asserted
with a active low pulse that has been externally
synchronized to CK_IN. Internally the DDF then uses this
start pulse to put the DDF in operate mode and start
accepting data inputs. When STARTIN is used to start the
DDF the ASTARTIN input must be tied high to prevent false
starts.
2
-2
-2
23
23
15
-16
8
0
.
2
22
2
22
-17
14
2
7
-1
2
21
2
21
-2
-18
19
2
13
6
-2
0
.
2
20
2
20
-19
18
2
2
12
5
-1
-3
2
19
2
19
-20
2
17
4
2
11
-2
-2
-4
15
3-205
0
2
18
2
18
-21
2
.
16
3
2
10
-3
-5
14
2
-1
2
17
2
17
-22
2
2
15
2
-4
9
2
13
-6
-2
2
16
2
16
-23
1
2
14
2
-5
2
8
12
-7
-3
2
13
2
2
-6
2
11
15
2
7
15
-8
-16
-4
0
FIR COEFFICIENT FORMAT
Fractional Two's Complement Output
2
12
.
Fractional Two's Complement Input
Fractional Two's Complement Input
2
-7
2
2
10
OUTPUT DATA FORMAT
14
6
14
2
-9
-17
-5
-1
INPUT DATA FORMAT
2
11
2
-8
2
2
2
-10
13
5
13
9
-18
-6
-2
HSP43220
2
FIGURE 11.
10
2
-9
2
2
2
-11
12
4
12
8
-19
-7
-3
2
-10
2
9
2
2
2
-12
3
11
11
7
-20
-8
-4
2
Multi-Chip Start Configurations
Since there are two methods to start up the DDF, there are also
two configurations that can be used to start up multiple chips.
The first method is shown in Figure 12. The timing of the
STARTOUT circuitry starts the second DDF on the same
clock as the first. If more DDFs are also to be started
synchronously, STARTOUT is connected to their STARTIN's.
The second method to start up DDFs in a multiple chip
configuration is to use the synchronous start scenario.
The STARTIN input is wired to all the chips in the chain, and is
asserted by a active low synchronous pulse that has been
externally synchronized to CK_IN. In this way all DDFs are
synchronously started. The ASTARTIN input on all the chips is
tied high to prevent false starts. The STARTOUT outputs are all
left unconnected. This configuration is illustrated in Figure 13.
-11
8
2
2
2
2
-13
2
6
10
10
-9
-21
-5
2
-12
7
2
2
2
-10
2
-14
1
5
-22
9
9
-6
2
-13
6
2
2
2
-11
2
-15
4
0
-23
8
8
-7
2
-14
5
2
2
-12
2
3
-24
7
7
-8
2
2
23
-16
-15
4
2
2
-13
2
2
-25
6
6
-9
2
22
-17
2
2
2
-14
1
2
-10
-26
5
5
-16
3
2
21
-18
2
2
2
-15
0
2
-11
-27
4
4
2
-17
2
20
-19
2
2
2
-12
2
-28
3
3
-18
1
19
-20
2
2
2
2
-13
-29
2
2
-19
0
18
-21
2
2
2
-14
-30
1
17
1
-22
2
2
2
16
-15
-31
0
-23
0