HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 6

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

There are three signals that control the integrator section;
they are H_STAGES, H_BYP and RESET. In Figure 2 these
control signals have been decoded and are labelled
INT_EN1 - INT_EN5. The order of the filter is loaded via the
control bus and is called H_STAGES. H_STAGES is
decoded to provide the enables for each integrator stage.
When a given integrator stage is selected, the feedback path
is enabled and the integrator accumulates the current data
sample with the previous sum. The integrator section can be
put in bypass mode by the H_BYP bit. When H_BYP or
RESET is asserted, the feedback paths in all integrator
stages are cleared.
Decimation Register
The output of the Integrator section is latched into the
Decimation Register by CK_DEC. The output of the
Decimation register is cleared when RESET is asserted. The
HDF decimation rate = H_DRATE +1, which is defined as
H
Comb Filter Section
The output of the Decimation Register is passed to the
Comb Filter Section. The Comb section consists of 5
cascaded Comb filters or differentiators. Each Comb filter
section calculates the difference between the current and
previous integrator output. Each Comb filter consists of a
register which is clocked by CK_DEC, followed by an
subtractor, where the subtractor calculates the difference
between the input and output of the register. Bit truncations
are done at each stage as shown in Figure 3. The first
stage bit width is 26 bits and the output of the fifth stage is
19 bits.
DEC
FROM
DECI-
MATION
REGISTER
CK_DEC
FROM
SHIFTER
CK
26
for convenience.
IN
COMB_EN5
66
RESET
REG
INT_EN5
MUX
B
A
A-B
3-199
REG
22
0
63
COMB_EN4
RESET
REG
INT_EN4
MUX
B
A
REG
A-B
0
21
53
FIGURE 3. COMB FILTER
FIGURE 2. INTEGRATOR
COMB_EN3
HSP43220
RESET
REG
INT_EN3
MUX
19
REG
B
A
There are three signals that control the Comb Filter; H_
STAGES, H_BYP and RESET. In Figure 3 these control
signals are decoded as COMB_EN1 - COMB_EN5. The
order of the Comb filter is controlled by H_STAGES, which is
programmed over the control bus. H_BYP is used to put the
comb section in bypass mode. RESET causes the register
output in each Comb stage to be cleared. The H_ BYP and
RESET control pins, when asserted force the output of all
registers to zero so data is passed through the subtractor
unaltered. When the H_STAGES control bits enable a given
stage the output of the register is subtracted from the input.
It is important to note that the Comb filter section has a speed
limitation. The Input sampling rate divided by the decimation
factor in the HDF (CK_IN/H
Violating this condition causes the output of the filter to be
incorrect. When the HDF is put in bypass mode this limitation
does not apply. Equation 1 describes the relationship between
F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK.
Rounder
The filter accuracy is limited by the 16-bit data input. To
maintain the maximum accuracy, the output of the comb is
rounded to 16 bits.
The Rounder performs a symmetric round of the 19-bit
output of the last Comb stage. Symmetric rounding is done
to prevent the synthesis of a 0Hz spectral component by the
rounding process and thus causing a reduction in spurious
free dynamic range. Saturation logic is also provided to
prevent roll over from the largest positive value to the most
negative value after rounding. The output of the last comb
filter stage in the HDF section has a 16-bit integer portion
with a 3-bit fractional part in 2's complement format.
0
A-B
43
20
COMB_EN2
RESET
INT_EN2
REG
MUX
REG
B
A
0
A-B
35
19
DEC
COMB_EN1
) should not exceed 4MHz.
INT_EN1
RESET
MUX
REG
REG
0
B
A
26
A-B
TO
DECIMATION
REGISTER
TO
ROUNDER