HSP43220 Intersil Corporation, HSP43220 Datasheet - Page 5

• Manufacturer Part Number: HSP43220
• Description: Decimating Digital Filter
• Manufacturer: Intersil Corporation

Pin Description
The HDF
The first filter section is called the High Order Decimation Filter
(HDF) and is optimized to perform decimation by large factors.
It implements a low pass filter using only adders and delay
elements instead of a large number of multiplier/ accumulators
that would be required using a standard FIR filter.
The HDF is divided into 4 sections: the HDF filter section,
the clock divider, the control register logic and the start logic
(Figure 1).
Data Shifter
After being latched into the Input Register the data enters the
Data Shifter. The data is positioned at the output of the shifter
to prevent errors due to overflow occurring at the output of the
HDF. The number of bits to shift is controlled by H_GROWTH.
STARTOUT
OUT_SELH
ASTARTIN
OUT_ENP
OUT_ENX
STARTIN
A0, A1
NAME
CK_DEC
CK_IN
DATA
IN
H_GROWTH
TYPE
16
O
A0-1
I
I
I
I
I
I
ISTART
6
INPUT
REG
Control Register Address. These lines are decoded to determine which control register is the destination for the data on
C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs.
ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational
mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT.
STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use
in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of
CK_IN.
STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on
the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's.
Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control
line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from
the accumulator output. Processing is not interrupted by this pin.
Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on
this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high imped-
ance state. Processing is not interrupted by this pin.
Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW
on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high
impedance state. Processing is not interrupted by this pin.
REGISTER LOGIC
(Continued)
CONTROL
INT_EN1-5
16
3-198
WR
H_GROWTH
SHIFTER
5
DATA
CS
6
COMB_EN1-5
C_BUS
66
FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE
5
H_DRATE
INTEGRATOR
H_BYP
INT_EN1-5
5
HDF FILTER SECTION
CK_IN
26
HSP43220
DIVIDER
CLOCK
CK DEC
RESET
DEC
REG
RESET
26
DESCRIPTION
Integrator Section
The data from the shifter goes to the Integrator section.
This is a cascade of 5 integrator (or accumulator) stages,
which implement a low pass filter. Each accumulator is
implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CK_IN as shown in Figure 2. The bit width of each integrator
stage goes from 66 bits at the first integrator down to 26 bits
at the output of the fifth integrator. Bit truncation is performed
at each integrator stage because the data in the integrator
stages is being accumulated and thus is growing, therefore
the lower bits become insignificant, and can be truncated
without losing significant data.
COMB FILTER
COMB_EN1-5
ISTART
5
RESET
19
CK_IN
START
LOGIC
ROUND
ASTARTIN
16
RESET
REG
STARTIN
STARTOUT
TO FIR
16
TO FIR