CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Timing Diagrams
Read Cycle Timing
Note:
16. On this diagram, when CE is LOW, CE
GW, BWE,BW
Data Out (Q)
ADDRESS
CLK
ADSP
ADSC
ADV
OE
[A:D]
CE
High-Z
[16]
t ADS
t AS
t CES
A1
t ADH
t CLZ
t
t AH
t CEH
t OEV
CH
t CDV
t CYC
Single READ
t
t CL
WES
1
Q(A1)
is LOW, CE
t
WEH
t OEHZ
t ADS
A2
2
t ADH
is HIGH and CE
t OELZ
t
ADVS
Q(A2)
t
t DOH
ADVH
t CDV
3
Q(A2 + 1)
is LOW. When CE is HIGH, CE
DON’T CARE
Q(A2 + 2)
ADV suspends burst.
UNDEFINED
BURST
READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
Q(A2)
Burst wraps around
to its initial state
Q(A2 + 1)
CY7C1214F
3
is HIGH.
Deselect Cycle
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Q(A2 + 2)
t CHZ