CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 11

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Timing Diagrams
Write Cycle Timing
Note:
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BW
BWE,
ADSP
ADSC
[A:D]
GW
ADV
CE
CLK
OE
BURST READ
High-Z
[16, 17]
t ADS
t CES
(continued)
t AS
A1
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst.
t CYC
t ADS
t
CL
t
Single WRITE
DS
D(A1)
t ADH
t
DH
A2
D(A2)
DON’T CARE
D(A2 + 1)
t
WES
BURST WRITE
t
WEH
D(A2 + 1)
UNDEFINED
[A:D]
ADV suspends burst.
LOW.
D(A2 + 2)
ADSC extends burst.
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t ADVS
Extended BURST WRITE
t WES
CY7C1214F
D(A3 + 1)
t ADVH
t WEH
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D(A3 + 2)