CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 4
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CY7C1214F-100AC
Manufacturer Part Number
CY7C1214F-100AC
Description
1-Mb (32K x 32) Flow-Through Sync SRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C1214F-100AC.pdf
(15 pages)
Document #: 38-05434 Rev. *A
Pin Descriptions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The CY7C1214F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP is ignored if CE
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP is asserted LOW. The addresses
V
V
MODE
NC
DDQ
SSQ
1
Name
is HIGH.
5,10,21,55
1,14,16,30
,38,39,42,
CDV
27,54,61,
,60,71,76
43,49,50,
51,66,80
4,11,20,
TQFP
70,77
31
) is 7.5 ns (117-MHz device).
,
(continued)
1
is HIGH.
I/O Ground
I/O Power
Supply
1
Input-
Static
, CE
I/O
1
, CE
2
, CE
1
, CE
2
, and CE
3
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
V
remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die.
DD
are all asserted
2
, CE
CDV
or left floating selects interleaved burst sequence. This is a strap pin and should
after clock
3
) and an
3
are all
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:D]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During byte writes, BWA controls DQA and BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os
are three-stated during a Byte Write. Since this is a common
I/O device, the asynchronous OE input signal must be
deasserted and the I/Os must be three-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are three-stated once a Write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the Write input signals (GW, BWE, and
BW[A:D]) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQs will be written
into the specified address location. Byte Writes are allowed.
During Byte Writes, BWA controls DQA, BWB controls DQB,
BWC controls DQC, and BWD controls DQD. All I/Os are
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQs. As a safety precaution, the
data lines are three-stated once a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1214F provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Description
1
, CE
2
, and CE
CY7C1214F
3
are all asserted
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