CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
LOW.
Interleaved Burst Address Table
(MODE = Floating or V
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a Read cycle all data bits are three-state when OE
Address
Parameter
(BW
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)
A1, A0
Cycle Description
First
00
01
10
11
A
, BW
B
, BW
[2, 3, 4, 5, 6]
C
, BW
Snooze mode standby current
Device operation to ZZ
ZZ Recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Address
Second
A1, A0
D
01
00
11
10
), BWE, GW = H.
ZZREC
DD
Address
External
External
External
)
Used
None
None
None
None
None
None
Description
Address
A1, A0
after the ZZ input returns
Third
10
00
01
11
CE
H
X
L
L
L
X
L
L
L
1
Address
CE
Fourth
A1, A0
H
X
X
X
X
X
L
L
L
10
01
00
11
3
A
, BW
CE
H
H
H
X
X
X
X
L
L
B
2
, BW
ZZ ADSP
H
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
L
L
L
L
L
L
L
L
C
, BW
Linear Burst Address Table (MODE = GND)
D
Address
Test Conditions
X
H
H
H
L
L
X
L
L
) and BWE = L or GW= L. WRITE = H when all Byte Write enable signals
DD
DD
A
First
1
00
01
10
11
– 0.2V
, A
– 0.2V
0
ADSC
X
X
X
X
X
L
L
L
L
Address
Second
ADV WRITE
A
X
X
X
X
X
X
X
X
X
[A: D]
1
01
10
11
00
, A
. Writes may occur only on subsequent clocks
0
X
X
X
X
X
X
X
X
L
2t
Min.
CYC
0
Address
A
Third
OE
H
X
X
X
X
X
X
X
L
1
10
11
00
01
, A
CY7C1214F
0
2t
2t
Max.
CLK
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Q
L-H Three-State
L-H D
40
CYC
CYC
X
Page 5 of 15
Three-State
Address
Fourth
A
DQ
1
00
01
10
11
Unit
, A
mA
ns
ns
ns
ns
0