CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Pin Descriptions
A0, A1, A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs
V
V
DD
SS
1
2
3
Name
A,
C,
BW
BW
B
D
82,99,100
37,36,32,
33,34,35,
44,45,46,
47,48,81,
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
13,18,19,
22,23,24,
25,28,29,
79,2,3,6,
7,8,9,12,
93,94,
15,41,
65, 91
17,40,
TQFP
95,96
67,90
88
87
89
98
97
92
86
83
84
85
64
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
Ground
Supply
Power
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address Inputs used to select one of the 32K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
sampled active. A
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of a
Read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A
are both asserted, only ADSP is recognized. ASDP is ignored when CE
HIGH
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
both asserted, only ADSP is recognized .
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by the addresses presented during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE . When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a
three-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
[A:D]
and BWE).
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are
[1:0]
[1:0]
2
1
1
and CE
and CE
and CE
feed the 2-bit counter.
are also loaded into the burst counter. When ADSP and ADSC
2
3
3
to select/deselect the device.
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device.
Description
CY7C1214F
1
, CE
2
1
, and CE
is deasserted
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