PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet - Page 3

• Manufacturer Part Number: PLL102-108XC
• Description: Programmable DDR Zero Delay Clock Driver
• Manufacturer: PLL [PhaseLink Corporation]

I2C BUS CONFIGURATION SETTING
I2C CONTROL REGISTERS
1. BYTE 0: Outputs Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Address Assignment
Data Transfer Rate
ceiver/Transmitter
Data Protocol
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Slave Re-
Pin#
39,40
43,44
46,47
22,23
19,20
9,10
5,6
2,3
A6
Provides both slave write and readback functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will termi-
nate the transfer. The write or read block both begins with the master sending a slave address
and a write condition (0xD4) or a read condition (0xD5).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
1
A5
1
Default
1
1
1
1
1
1
1
1
A4
Programmable DDR Zero Delay Clock Driver
0
Description
CLKT7, CLKC7 (1= active, 0=inactive)
CLKT6, CLKC6 (1= active, 0=inactive)
CLKT5, CLKC5 (1= active, 0=inactive)
CLKT4, CLKC4 (1= active, 0=inactive)
CLKT3, CLKC3 (1= active, 0=inactive)
CLKT2, CLKC2 (1= active, 0=inactive)
CLKT1, CLKC1 (1= active, 0=inactive)
CLKT0, CLKC0 (1= active, 0=inactive)
A3
1
A2
0
A1
0
A0
1
PLL102-108
R/W
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Rev 03/29/02 Page 3