PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet - Page 5

• Manufacturer Part Number: PLL102-108XC
• Description: Programmable DDR Zero Delay Clock Driver
• Manufacturer: PLL [PhaseLink Corporation]

4. BYTE 3: Outputs Register (1=Enable, 0=Disable)
TABLE 2: CLK_INT Delay Programming Summary:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit<3:0>
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CLKINT
FBOUT
Delay
Skew
Name
-
CLK_INT to CLK Delay
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
+2,550 ps
+2,380 ps
+2,210 ps
+2,040 ps
+1,870 ps
+1,700 ps
+1,530 ps
+1,360 ps
+1,190 ps
+1,020 ps
+850 ps
+680 ps
+510 ps
+340 ps
+170 ps
Default
Default
1
0
1
1
0
0
0
0
Programmable DDR Zero Delay Clock Driver
Reserved
These three bits will adjust timing of FBOUTT signal either positive
or negative delay up to +800ps or –600ps with 200ps per step.
(see Table 1)
These four bits will program the propagation delay from CLK_INT
to the input of PLL within the range between 0ps and 2.5ns with
170ps step size. (see Table 2)
Description
PLL102-108
Rev 03/29/02 Page 5