PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet - Page 4

• Manufacturer Part Number: PLL102-108XC
• Description: Programmable DDR Zero Delay Clock Driver
• Manufacturer: PLL [PhaseLink Corporation]

TABLE 1: Output Signals SKEW Programming Summary:
2. BYTE 1: SKEW Register (1=Enable, 0=Disable)
3. BYTE 2: SKEW Register (1=Enable, 0=Disable)
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Bit<2:0>
111
110
101
100
011
010
001
000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Default
+400ps
+300ps
+200ps
+100ps
-100ps
-200ps
-300ps
DDR Skew Setting ( 100ps/step)
DDRA
DDRB
DDRC
DDRD
FBOUT-SKEWEN
Skew
Skew
Skew
Skew
DDR-SKEWEN
Name
Name
26,27
29,30
Setting applies to the following
outputs:
1. DDRA: CLK0, CLK1, CLK5
2. DDRB: CLK7, CLK8, CLK9
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
3. DDRC: CLK2, CLK3, CLK4
4. DDRD: CLK6
Default
Default
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
Programmable DDR Zero Delay Clock Driver
CLKT9, CLKC9 (1= active, 0=inactive)
CLKT8, CLKC8 (1= active, 0=inactive)
These three bits will adjust timing of DDRA signals (CLK0, CLK1,
CLK5) either positive or negative delay up to +400ps or –300ps
with 100ps per step. (see Table 1)
These three bits will adjust timing of DDRB signals (CLK7, CLK8,
CLK9) either positive or negative delay up to +400ps or –300ps
with 100ps per step. (see Table 1)
1= disable, 0= enable
1= disable, 0= enable
These three bits will adjust timing of DDRC signals (CLK2, CLK3,
CLK4) either positive or negative delay up to +400ps or –300ps
with 100ps per step. (see Table 1)
These three bits will adjust timing of DDRD signals (CLK6) either
positive or negative delay up to +400ps or –300ps with 100ps per
step. (see Table 1)
FBOUT Skew Setting ( 200ps/step)
Default
+800ps
+600ps
+400ps
+200ps
-200ps
-400ps
-600ps
Description
Description
Setting applies to the following out-
puts:
1. FB_OUTT
PLL102-108
Rev 03/29/02 Page 4