PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet - Page 2

• Manufacturer Part Number: PLL102-108XC
• Description: Programmable DDR Zero Delay Clock Driver
• Manufacturer: PLL [PhaseLink Corporation]

PIN DESCRIPTIONS
Functionality
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
2.5V (Nom)
2.5V (Nom)
CLKC(0:9)
CLKT(0:9)
FB_OUTT
CLK_INT
FB_INT
SDATA
AVDD
Name
AGND
AVDD
SCLK
GND
GND
VDD
GND
N/C
4,11,15,21,28,34,
3,5,10,20,22,46,
2,6,9,19,23,47,
25,31,41,42,48
CLK_INT
1,7,8,18,24,
44,39,29,27
43,40,30,26
INPUTS
Number
14,32,36
38,45
H
H
L
L
16
17
13
33
35
37
12
CLK_INC
Type
O
P
P
P
P
B
I
I
I
I
I
H
H
L
L
Programmable DDR Zero Delay Clock Driver
2.5V power supply.
Ground
Analog power supply (2.5V).
Analog ground.
“True” clocks of differential pair outputs.
“Complementary” clocks of differential pair outputs.
Single-ended 3.3V tolerant input.
Not connected.
“True” feedback output. Dedicated for external feedback. It switches at the
same frequency as the CLK_INT.
“True” feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Serial data input for serial interface port.
CLKT
H
H
L
L
OUTPUTS
CLKC
Description
H
H
L
L
FB_OUTT
PLL102-108
H
H
L
L
Rev 03/29/02 Page 2
Bypass/Off
Bypass/Off
PLL State
On
On