AD9775EB AD [Analog Devices], AD9775EB Datasheet

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FEATURES 14-Bit Resolution, 160/400 MSPS Input/Output Data Rate Selectable Interpolating Filter Programmable Channel Gain and Offset Adjustment f / Digital Quadrature Modulation S S Capability Direct IF Transmission Mode for 70 MHz + IFs ...

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AD9775 (continued from page 1) errors associated with analog quadrature modulators. The gain adjustment range can also be used to control the output power level of each DAC. The AD9775 features the ability to perform f digital ...

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AD9775–SPECIFICATIONS ( MIN DC SPECIFICATIONS otherwise noted.) Parameter RESOLUTION 1 DC Accuracy Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT (for IR and 2R Gain Setting Modes) Offset Error Gain Error (With Internal Reference) Gain Matching 2 Full-Scale Output Current ...

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AD9775 DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (f Output Settling Time (t ) (to 0.025%) ST Output Rise Time (10% to 90%)* Output Fall Time (10% to 90%)* Output Noise ( mA) OUTFS AC ...

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... Model Range Description AD9775BSV –40°C to +85°C 80-Lead TQFP AD9775EB Evaluation Board *SV = Thin Plastic Quad Flatpack CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9775 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

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AD9775 CLKVDD LPF CLKVDD CLKGND CLK+ CLK– CLKGND DATACLK/PLL_LOCK DGND DVDD P1B13 (MSB) P1B12 P1B11 P1B10 P1B9 P1B8 DGND DVDD P1B7 P1B6 CONNECT PIN CONFIGURATION ...

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Pin Number Mnemonic 1, 3 CLKVDD 2 LPF 4, 7 CLKGND 5 CLK+ 6 CLK– 8 DATACLK/PLL_LOCK 9, 17, 25, 35, 44, 52 DGND 10, 18, 26, 36, 43, 51 DVDD 11–16, 19–24, 27, 28 P1B13 (MSB) to P1B0 (LSB) ...

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AD9775 DIGITAL FILTER SPECIFICATIONS Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient – –134 244 10, ...

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DEFINITIONS OF SPECIFICATIONS Adjacent Channel Power Ratio (ACPR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF ...

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AD9775 –Typical Performance Characteristics ( AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Doubly Terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – 130 ...

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C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Doubly Terminated, unless otherwise noted.) 90 –6dBFS 85 –3dBFS 80 75 0dBFS ...

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AD9775 ( AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Doubly Terminated, unless otherwise noted.) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 FREQUENCY – ...

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MODE CONTROL (VIA SPI PORT) Address Bit 7 Bit 6 Bit 5 00h SDIO LSB, MSB First Software Reset on Bidirectional 0 = MSB Logic “1” Input 1 = LSB 1 = I/O 01h Filter Filter Modulation Interpolation ...

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AD9775 REGISTER DESCRIPTION Address 00h Bit 7 Logic “0” (default). Causes the SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to “1,” SDIO can act as an input or ...

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Address 03h Bits 1, 0 Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ...

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AD9775 FUNCTIONAL DESCRIPTION The AD9775 dual interpolating DAC consists of two data chan- nels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architec- ture. Each channel includes three FIR filters, ...

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R/W Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic “0” indicates a write operation. N1, N0 Bits 6 and 5 ...

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AD9775 t CS SCLK SDIO Figure 4. Timing Diagram for Register Write to AD9775 CS SCLK SDIO SDO Figure 5. Timing Diagram for Register Read from AD9775 NOTES ON SERIAL PORT OPERATION The AD9775 serial port configuration bits reside in ...

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The offset control defines a small current that can be added (not both) on the IDAC and QDAC. The selec- OUTA OUTB tion of which I this offset current is directed toward is OUT programmable via ...

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AD9775 0 –10 OFFSET REGISTER 1 ADJUSTED –20 –30 –40 –50 –60 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET –70 REGISTER 1 SET TO OPTIMIZED VALUE –80 –1024 –768 –512 –256 0 256 DAC1, DAC2 – Offset Register Codes Figure 9. ...

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CLK+ CLK– PLL_LOCK 1 = LOCK AD9775 LOCK INTERPOLATION PHASE FILTERS, DETECTOR MODULATORS, AND DACS CLOCK PRESCALER INPUT DISTRIBUTION DATA CIRCUITRY LATCHES INTERNAL SPI CONTROL REGISTERS INTERPOLATION RATE MODULATION CONTROL RATE CONTROL SPI ...

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AD9775 76 (MOD. ON) 75 (MOD. ON) 75.0 74 74.0 73.5 73.0 72.5 72 100 f – MHz DATA Figure 16. I vs. f vs. Interpolation Rate, AVDD DATA PLL Disabled 35 ...

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OD CLKIN DATACLK DATA AT PORTS 1 AND Figure 18. Timing Requirements in Two Port Input Mode, with PLL Enabled DATACLK DRIVER STRENGTH (Control Register 02h, Bit 5) The DATACLK output driver strength is ...

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AD9775 IQ PAIRING (Control Register 02h, Bit 0) In one port mode, the interleaved data is latched into the AD9775 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this ...

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The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the previous section (PLL Enabled, One Port Mode) have identical functionality with the PLL disabled CLKIN ONEPORTCLK I AND Q INTERLEAVED INPUT DATA AT PORT ...

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AD9775 MODULATION, NO INTERPOLATION With Control Register 01h, Bits 7 and 6 set to “00,” the inter- polation function on the AD9775 is disabled. Figures 25a–25d show the DAC output spectral characteristics of the AD9775 in the various modulation modes, ...

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MODULATION, INTERPOLATION = 2× With Control Register 01h, Bits 7 and 6 set to “01,” the inter- polation rate of the AD9775 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (1, ...

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AD9775 MODULATION, INTERPOLATION = 4× With Control Register 01h, Bits 7 and 6 set to “10,” the inter- polation rate of the AD9775 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output 0 –20 –40 ...

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MODULATION, INTERPOLATION = 8× With Control Register 01h, Bits 7 and 6 set to “11,” the interpolation rate of the AD9775 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, 0.707, ...

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AD9775 10 ZERO STUFFING 0 –10 –20 ZERO STUFFING –30 DISABLED –40 –50 0 0.5 1 NORMALIZED TO f WITH ZERO STUFFING OUT DATA DISABLED – Hz Figure 29. Effect of Zero Stuffing on DAC’s SIN(x)/ x Response ...

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The entire upconversion, from baseband to transmit frequency, is represented graphically in Figure 33. The resulting spectrum shown in Figure 33 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative ...

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AD9775 COMPLEX BASEBAND SIGNAL 2)t OUTPUT = REAL 1/2 = REAL – 1 – Figure 34. Two-Stage Complex Upconversion IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS As shown in Figure 33, image ...

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The complex carrier synthesized in the AD9775 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running result, complex modulation only functions DAC ...

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AD9775 0 – –40 –60 –80 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 (LO OUT DATA Figure 37. 2 × Interpolation, Complex f 0 – –40 ...

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FREQUENCY – MHz Figure 43. AD9775, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = Modulation in ...

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AD9775 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY – MHz Figure 47. AD9775, Real DAC Output of Complex Input Signal Near Baseband (Negative Frequencies Only), Interpolation = 4 , Complex Modulation ...

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APPLYING THE AD9775 OUTPUT CONFIGURATIONS The following sections illustrate typical output configurations for the AD9775. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration ...

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AD9775 of the AD9775 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp’s differential gain, its gain setting resistor values, and full-scale output swing capa- bilities should all be considered when optimizing this circuit. R ...

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INPUT CLOCK AWG2021 DG2020 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – Figure 55. Test Configuration for AD9775 in Two Port Mode with PLL ...

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AD9775 INPUT CLOCK AWG2021 DG2020 JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – Figure 57. Test Configuration for AD9775 in Two Port Mode with ...

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O1P O1N C54 DNP L5 L4 DNP DNP C73 DNP ADTL1- R36 R35 51 51 J20 C77 R37 C80 100pF DNP DNP T4 ETC1-1-13 DNP J21 J7 VDDMIN W11 W12 DVDD_IN J8 J5 AVDD_IN J4 J6 CLKVDD_IN ...

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AD9775 Figure 60. AD9775 Clock, Power Supplies, and Output Circuitry –42– REV. 0 ...

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Figure 61. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry REV. 0 –43– AD9775 ...

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AD9775 DATA-B RCON ...

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Figure 63. AD9775 Evaluation Board Components, Top Side Figure 64. AD9775 Evaluation Board Components, Bottom Side REV. 0 –45– AD9775 ...

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AD9775 Figure 65. AD9775 Evaluation Board Layout, Layer One (Top) Figure 66. AD9775 Evaluation Board Layout, Layer Two (Ground Plane) –46– REV. 0 ...

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Figure 67. AD9775 Evaluation Board Layout, Layer Three (Power Plane) Figure 68. AD9775 Evaluation Board Layout, Layer Four (Bottom) REV. 0 –47– AD9775 ...

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AD9775 80-Lead, Thermally Enhanced, Thin Plastic Quad Flatpack [TQFP] 1.20 (0.0472) MAX 0.75 (0.0295) 0.60 (0.0236) 80 0.45 (0.0177) 1 SEATING PLANE PIN 1 20 COPLANARITY 21 0.15 (0.0059) 0.05 (0.0020) 0.20 (0.0079) 0.09 (0.0035) 0.50 (0.0197) CONTROLLING DIMENSIONS ARE ...