AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 7

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

REV. 0
Pin Number
1, 3
2
4, 7
5
6
8
9, 17, 25, 35, 44, 52
10, 18, 26, 36, 43, 51
11–16, 19–24, 27, 28
29, 30, 49, 50
31
32
33, 34, 37–42, 45–48
53
54
55
56
57
58
59
60
61, 63, 65, 76, 78, 80
62, 64, 66, 67, 70, 71, AGND
74, 75, 77, 79
68, 69
72, 73
Mnemonic
CLKVDD
LPF
CLKGND
CLK+
CLK–
DATACLK/PLL_LOCK
DGND
DVDD
P1B13 (MSB) to P1B0 (LSB) Port “1” Data Inputs
NC
IQSEL/P2B13 (MSB)
ONEPORTCLK/P2B12
P2B11 to P2B0 (LSB)
SPI_SDO
SPI_SDIO
SPI_CLK
SPI_CSB
RESET
REFIO
FSADJ2
FSADJ1
AVDD
I
I
OUTA2
OUTA1
, I
, I
OUTB2
OUTB1
PIN FUNCTION DESCRIPTIONS
Description
Clock Supply Voltage
PLL Loop Filter
Clock Supply Common
Differential Clock Input
Differential Clock Input
With the PLL enabled, this pin indicates the state of the PLL. A read of a
Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the
PLL has not achieved lock. This pin may also be programmed to act as
either an input or output (Address 02h, Bit 3) DATACLK signal running at
the input data rate.
Digital Common
Digital Supply Voltage
No Connect
In “1” port mode, IQSEL = 1 followed by a rising edge of the differential
input clock will latch the data into the I channel input register. IQSEL = 0
will latch the data into the Q channel input register. In “2” port mode, this
pin becomes the port “2” MSB.
With the PLL disabled and the AD9775 in “1” port mode, this pin becomes
a clock output that runs at twice the input data rate of the I and Q channels.
This allows the AD9775 to accept and demux interleaved I and Q data to
the I and Q input registers.
Port “2” Data Inputs
In the case where SDIO is an input, SDO acts as an output. When SDIO
becomes an output, SDO enters a High-Z state.
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register
Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.
Data input to the SPI port is registered on the rising edge of SPI_CLK.
Data output on the SPI port is registered on the falling edge.
Chip Select/SPI Data Synchronization. On momentary logic high, resets
SPI port logic and initializes instruction cycle.
Logic “1” resets all of the SPI port registers, including Address 00h, to their
default values. A software reset can also be done by writing a Logic “1” to
SPI Register 00h, Bit 5. However, the software reset has no effect on the bits
in Address 00h.
Reference Output, 1.2 V Nominal
Full-Scale Current Adjust, Q Channel
Full-Scale Current Adjust, I Channel
Analog Supply Voltage
Analog Common
Differential DAC Current Outputs, Q Channel
Differential DAC Current Outputs, I Channel
–7–
AD9775