AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 21

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

In addition, if the zero stuffing option is enabled, the VCO will
double its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 14 illustrates typical phase noise per-
formance of the AD9775 with 2× interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of f
repetitive nature of this signal eliminated quantization noise and
distortion spurs as a factor in the measurement. Although the
curves blend together in Figure 14, the different conditions are
called out here for clarity.
REV. 0
INTERPOLATION
LATCHES
INTERPOLATION
LATCHES
CONTROL
Figure 13. PLL and Clock Circuitry with PLL Disabled
INPUT
Figure 12. PLL and Clock Circuitry with PLL Enabled
DATA
CONTROL
INPUT
DATA
RATE
RATE
f
125 MSPS
125 MSPS
100 MSPS
75 MSPS
50 MSPS
DATA
1
1
2
0 = NO LOCK
0 = NO LOCK
2
PLL_LOCK
DISTRIBUTION
PLL_LOCK
INTERPOLATION
1 = LOCK
MODULATORS,
DISTRIBUTION
INTERPOLATION
1 = LOCK
CIRCUITRY
INTERNAL SPI
MODULATORS,
CIRCUITRY
INTERNAL SPI
REGISTERS
AND DACS
4
SPI PORT
CLOCK
CONTROL
REGISTERS
FILTERS,
AND DACS
4
SPI PORT
CLOCK
CONTROL
FILTERS,
8
8
PLL
Disabled
Enabled
Enabled
Enabled
Enabled
CLK+
MODULATION
CLK+
MODULATION
CONTROL
CONTROL
RATE
RATE
CLK–
CLK–
PRESCALER
DETECTOR
PRESCALER
DETECTOR
PHASE
PHASE
AD9775
Prescaler Ratio
div1
div2
div2
div4
CONTROL
(PLL ON)
CONTROL
(PLL ON)
(PRESCALER)
PLL DIVIDER
AD9775
PLL
(PRESCALER)
PLL DIVIDER
PLL
CONTROL
CHARGE
CONTROL
CHARGE
PUMP
VCO
PUMP
VCO
PLLVDD
DATA
/4. The
LPF
–21–
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9775. This will suffice unless
the input data rate is below 10 MHz, in which case an external
series RC is required between the LPF and PLLVDD pins.
POWER DISSIPATION
The AD9775 has three voltage supplies: AVDD, DVDD, and
CLKVDD. Figures 15, 16, and 17 show the current required
from each of these supplies when each is set to the 3.3 V nominal
specified for the AD9775. Power dissipation (P
extracted by multiplying the given curves by 3.3. As Figure 15
shows, I
lation rate, and the activation of the internal digital modulator.
I
by itself. In Figure 16, I
to the data, the interpolation rate, and the modulator function
but to a much lesser degree (<10%). In Figure 17, I
varies over a wide range yet is responsible for only a small per-
centage of the overall AD9775 supply current requirements.
DVDD
, however, is relatively insensitive to the modulation rate
Figure 15. I
PLL Disabled
–100
–110
DVDD
–10
–20
–30
–40
–50
–60
–70
–80
–90
400
350
300
250
200
150
100
50
0
0
0
0
Figure 14. Phase Noise Performance
is very dependent on the input data rate, the interpo-
8
DVDD
,
1
8
(MOD. ON)
50
AVDD
vs. f
FREQUENCY OFFSET – MHz
4
DATA
shows the same type of sensitivity
,
4
2
(MOD. ON)
f
DATA
vs. Interpolation Rate,
100
– MHz
3
2
150
D
,
AD9775
4
(MOD. ON)
) can easily be
1
2
CLKVDD
200
5