AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 15

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

Address 03h
Bits 1, 0
Address 04h
Bit 7
Bit 6
Bits 0, 1, 2 With the charge pump control set to manual, these
Equation 1 shows I
mode, the current I
scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.
REV. 0
I
I
I
OUTA
OUTB
OFFSET
=
=
Setting this divide ratio to a higher number allows
the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output clocks
run substantially slower. The divider ratio is set
according to the following table:
00
01
10
11
Logic “0” (default) disables the internal PLL. Logic
“1” enables the PLL.
Logic “0” (default) sets the charge pump control to
automatic. In this mode, the charge pump bias
current is controlled by the divider ratio defined in
Address 03h, Bits 1 and 0. Logic “1” allows the
user to manually define the charge pump bias cur-
rent using Address 04h, Bits 2, 1, and 0. Adjusting
the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.
bits define the charge pump bias current according
to the following table:
000
001
010
011
100
= ×












4
6
6
×
×
I
OUTA
8
8
REF
I
I
REF
REF
REF
50 µA
100 µA
200 µA
400 µA
800 µA
1
2
4
8
is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a









and I
OFFSET






COARSE
COARSE
1024
OUTB
16
16



as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R
+
+
1
1






–
–






3
3
×
×
32
32
I
I
REF
REF










 

FINE
FINE
256
256







 ×


 ×

–15–













Address 05h, 09h
Bits 7–0
Address 06h, 0Ah
Bits 3–0
Address 07h, 0Bh
Bits 7–0
Address 08h, 0Ch
Bit 1, 0
Address 08h, 0Ch
Bit 7
1024
1024
24
24












DATA
2
14
2
These bits represent an 8-bit binary number (Bit 7
MSB) that defines the fine gain adjustment of the I
(05h) and Q (09h) DAC, according to the equation
given below.
These bits represent a 4-bit binary number (Bit 3 MSB)
that defines the coarse gain adjustment of the I (06h)
and Q (0Ah) DACs according to the equation below.
The 10 bits from these two address pairs (07h, 08h
and 0Bh, 0Ch) represent a 10-bit binary number
that defines the offset adjustment of the I and Q
DACs according to the equation below (07h, 0Bh–Bit
7 MSB/08h, 0Ch–Bit 0 LSB)
This bit determines the direction of the offset of the
I (08h) and Q (0Ch) DACs. A Logic “0” will apply
a positive offset current to I
will apply a positive offset current to I
magnitude of the offset current is defined by the
bits in Addresses 07h, 0Bh, 08h, and 0Ch accord-
ing to the formulas given below.
14
–
DATA
2



14



–
1







OUTA
, while a Logic “1”
AD9775
OUTB
. The
(1)