AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 24

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

AD9775
IQ PAIRING
(Control Register 02h, Bit 0)
In one port mode, the interleaved data is latched into the
AD9775 internal I and Q channels in pairs. The order of how
the pairs are latched internally is defined by this control register.
The following is an example of the effect this has on incoming
interleaved data.
Given the following interleaved data stream, where the data
indicates the value with respect to full scale:
I
0.5
With the control register set to “0” (I first), the data will appear
at the internal channel inputs in the following order in time:
With the control register set to “1” (Q first), the data will appear at
the internal channel inputs in the following order in time:
The values x and y represent the next I value and the previous
Q value in the series.
PLL DISABLED, TWO PORT MODE
With the PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal clock dividers in the AD9775 syn-
thesize the DATACLK signal at Pin 8, which runs at the input
data rate and can be used to synchronize the input data. Data is
latched into input Ports 1 and 2 of the AD9775 on the rising edge
of DATACLK. DATACLK speed is defined as the speed of
CLKIN divided by the interpolation rate. With zero stuffing
enabled, this division increases by a factor of 2. Figure 21
illustrates the delay between the rising edge of CLKIN and the
rising edge of DATACLK, as well as t
The programmable modes DATACLK inversion and DATACLK
driver strength described in the previous section (PLL
Enabled, Two Port Mode) have identical functionality with
the PLL disabled.
As described earlier in the PLL-Enabled Mode section, t
vary depending on CLKIN frequency and interpolation rate.
However, with the PLL disabled, the input data latches are
closely synchronized to DATACLK so that it is recommended
in this mode that the input data be timed from DATACLK, not CLKIN.
I Channel
Q Channel
I Channel
Q Channel
Q
0.5
I
1
0.5
0.5
0.5
y
Q
1
I
0.5
1
0.5
1
1
Q
0.5
0.5
1
0.5
0.5
I
0
S
and t
0
0.5
Q
0
H
0
0
in this mode.
0.5
0
I
0.5
0.5
0.5
Q
0.5
OD
x
0.5
can
–24–
PLL DISABLED, ONE PORT MODE
In one port mode, data is received into the AD9775 as an inter-
leaved stream on Port 1. A clock signal (ONEPORT CLK),
running at the interleaved data rate which is 2× the input data
rate of the internal I and Q channels is available for data syn-
chronization at Pin 32.
With PLL disabled, a clock at the DAC output rate must be applied
to CLKIN. Internal dividers synthesize the ONEPORTCLK
signal at Pin 32. The selection of the data for the I or Q channel
is determined by the state of the logic level applied to Pin 31
(IQSEL when the AD9775 is in one port mode) on the rising
edge of ONEPORTCLK. IQSEL = 1 under these conditions
will latch the data into the I channel on the clock rising edge,
while IQSEL = 0 will latch the data into the Q channel. It is
possible to invert the I and Q selection by setting control
Register 02h, Bit 1 to the invert state (Logic “1”). Figure 22
illustrates the timing requirements for the data inputs as well as
the IQSEL input. Note that the 1 interpolation rate is not
available in the one port mode.
One port mode is very useful when interfacing with devices
such as Analog Devices’ AD6622 or AD6623 transmit signal
processors, in which two digital data channels have been inter-
leaved (multiplexed).
DATA AT PORTS
Figure 21. Timing Requirements in Two Port
Input Mode with PLL Disabled
1 AND 2
DATACLK
CLKIN
t
OD
t
S
t
H
t
t
(TYP SPECS)
S
H
= 5.0ns
= –3.2ns
REV. 0