AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 20

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

AD9775
1R/2R MODE
In the 2R mode, the reference current for each channel is set
independently by the FSADJ resistor on that channel. The AD9775
can be programmed to derive its reference current from a single
resistor on Pin 60 by placing the part in the 1R mode. The trans-
fer functions in Equation 1 are valid for the 2R mode. In the
1R mode, the current developed in the single FSADJ resistor is
split equally between the two channels. The result is that in the
1R mode, a scale factor of one-half must be applied to the for-
mulas in Equation 1. The full-scale DAC current in the 1R mode
can still be set to as high as 20 mA by using the internal 1.2 V
reference and a 950 Ω resistor, instead of the 1.9 kΩ resistor
typically used in the 2R mode.
CLOCK INPUT CONFIGURATIONS
The clock inputs to the AD9775 can be driven differentially or
single-ended. The internal clock circuitry has supply and ground
(CLKVDD, CLKGND) separate from the other supplies on the
chip to minimize jitter from internal noise sources.
Figure 10 shows the AD9775 driven from a single-ended clock
source. The CLK+/CLK– Pins form a differential input (CLKIN),
so that the statically terminated input must be dc-biased to the
midswing voltage level of the clock driven input.
A configuration for differentially driving the clock inputs is given
in Figure 11. DC-blocking capacitors can be used to couple a
clock driver output whose voltage swings exceed CLKVDD or
CLKGND. If the driver voltage swings are within the supply
range of the AD9775, the dc-blocking capacitors and bias resistors
are not necessary.
Figure 10. Single-Ended Clock Driving Clock Inputs
Figure 9. Offset Adjust Control, Effect on LO
Suppression
–10
–20
–30
–40
–50
–60
–70
–80
–1024
0
–768
V
THRESHOLD
DAC1, DAC2 – Offset Register Codes
–512
–256
OFFSET REGISTER 1 ADJUSTED
AD9775
R
0.1µF
SERIES
0
OFFSET REGISTER 2
ADJUSTED, WITH OFFSET
REGISTER 1 SET
TO OPTIMIZED VALUE
256
CLK+
CLKVDD
CLK–
CLKGND
512
768
1024
–20–
A transformer, such as the T1-1T from Mini-Circuits, can also
be used to convert a single-ended clock to differential. This
method is used on the AD9775 evaluation board so that an exter-
nal sine wave with no dc offset can be used as a differential clock.
PECL/ECL drivers require varying termination networks, the
details of which are left out of Figures 10 and 11 but can be found
in application notes such as AND8020/D from On Semiconductor.
These networks depend on the assumed transmission line imped-
ance and power supply voltage of the clock driver. Optimum
performance of the AD9775 is achieved when the driver is placed
very close to the AD9775 clock inputs, thereby negating any
transmission line effects such as reflections due to mismatch.
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver cir-
cuitry should provide the AD9775 with a low jitter clock input
that meets the min/max logic levels while providing fast edges.
Although fast clock edges help minimize any jitter that will manifest
itself as phase noise on a reconstructed waveform, the high gain
bandwidth product of the AD9775’s differential comparator can
tolerate sine wave inputs as low as 0.5 V p-p, with minimal
degradation of the output noise floor.
PROGRAMMABLE PLL
CLKIN can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled) according
to the state of Address 02h, Bit 7 in the SPI port register. The
internal operation of the AD9775 clock circuitry in these two
modes is illustrated in Figures 12 and 13.
The PLL clock multiplier and distribution circuitry produce the
necessary internal synchronized 1×, 2×, 4×, and 8× clocks for
the rising edge triggered latches, interpolation filters, modula-
tors, and DACs. This circuitry consists of a phase detector,
charge pump, voltage controlled oscillator (VCO), prescaler,
clock distribution, and SPI port control. The charge pump and
VCO are powered from PLLVDD while the differential clock
input buffer, phase detector, prescaler, and clock distribution
are powered from CLKVDD. PLL lock status is indicated by
the logic signal at the PLL_LOCK Pin, as well as by the status of
Bit 1, Register 00h. To ensure optimum phase noise performance
from the PLL clock multiplier and distribution, PLLVDD and
CLKVDD should originate from the same clean analog supply.
The speed of the VCO with the PLL enabled also has an effect
on phase noise. Optimal phase noise with respect to VCO speed
is achieved by running the VCO in the range of 450 MHz to
550 MHz. The VCO speed is a function of the input data rate,
the interpolation rate, and the VCO prescaler, according to the
following function:
VCO Speed MHz
Input Data Rate MHz
Figure 11. Differential Clock Driving Clock Inputs
(
ECL/PECL
(
AD9775
)
=
0.1 F
0.1 F
0.1 F
)
×
InterpolationRate
1k
1k
1k
1k
CLK+
CLKVDD
CLK–
CLKGND
× Pr
escaler
REV. 0