KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 15

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 26 through 28. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 26 and 27.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5512P-50 is 500Ω.
The SHA design uses a switched capacitor input stage (see
Figure 40), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
FIGURE 27. TRANSMISSION-LINE TRANSFORMER INPUT
1000pF
1000pF
1000pF
ADT1-1WT
1.8
1.4
1.0
0.6
0.2
FIGURE 25. ANALOG INPUT RANGE
ADTL1-12
PURPOSE APPLICATIONS
FOR HIGH IF APPLICATIONS
0.725V
ADTL1-12
ADT1-1WT
15
INP
0.1µF
0.1µF
INN
VCM
0.535V
VCM
KAD5512P
KAD5512P
VCM
KAD5512P-50
A differential amplifier, as shown in Figure 28, can be used in
applications that require DC-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 41).
Driving these inputs with a high level (up to 1.8V
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 29. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2X frequency divider is provided in series with
the clock input. The divider can be used in the 2X mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 19.
AVDD
49.9O
0.22µF
200pF
Ω
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
FIGURE 29. RECOMMENDED CLOCK DRIVE
CLKDIV PIN
69.8O
69.8O
AVDD
AVSS
Float
1kO
TABLE 1. CLKDIV PIN SETTINGS
Ω
100O
100O
Ω
TC4-1W
Ω
Ω
Ω
348O
348O
1000pF
CM
1kO
Ω
Ω
Ω
0.1µF
DIVIDE RATIO
25O
25O
Not Allowed
Ω
Ω
217O
200pF
200pF
200O
2
1
Ω
Ω
P-P
January 16, 2009
KAD5512P
on each
FN6805.0
VCM
CLKP
CLKN