KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 23

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

SPI Memory Map
76-BF
03-07
11-1F
26-5F
60-6F
(Hex)
Addr
00
01
02
08
09
10
20
21
22
23
24
25
70
71
72
73
74
75
device_index_A
output_mode_A
output_mode_B
gain_medium
offset_coarse
config_status
chip_version
gain_coarse
Parameter
port_config
phase_slip
offset_fine
burst_end
skew_diff
gain_fine
reserved
reserved
reserved
reserved
reserved
reserved
chip_id
modes
Name
23
(MSB)
Active
Bit 7
SDO
other codes = reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
1 = slow
0 = fast
clock_divide
Range
Result
Bit 6
XOR
LSB
First
DLL
Reserved
Reset
TABLE 17. SPI MEMORY MAP
Bit 5
Soft
Reserved
KAD5512P-50
Burst end address [7:0]
Reserved
Bit 4
Differential Skew
Chip Version #
Coarse Offset
Medium Gain
Fine Offset
Fine Gain
Reserved
Reserved
Chip ID #
Reserved
Reserved
Reserved
Reserved
Bit 3
Mirror
(bit5)
Bit 2
Power-Down Mode [2:0]
001 = Twos Complement
001 = Normal Operation
other codes = reserved
other codes = reserved
other codes = reserved
Coarse Gain
Output Format [2:0]
100 = Offset Binary
Clock Divide [2:0]
000 = Pin Control
000 = Pin Control
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
010 = Gray Code
100 = Sleep
010 = Nap
ADC01
Mirror
(bit6)
Bit 1
ADC00
(LSB)
Mirror
Clock
(bit7)
Edge
Bit 0
Next
affected by
affected by
affected by
affected by
Def. Value
Read Only
Soft Reset
Soft Reset
Read only
Read only
cal. value
cal. value
cal. value
cal. value
cal. value
(Hex)
Reset
Reset
NOT
NOT
NOT
NOT
Soft
Soft
00h
00h
00h
00h
80h
00h
00h
00h
00h
January 16, 2009
Indexed/
Global
FN6805.0
G
G
G
G
G
G
G
G
G
G
I
I
I
I
I
I
I