KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 20

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

During a write operation, the user must be cautious to
transmit the correct number of bytes based on the starting
and ending addresses.
Bits 7:0 Burst End Address
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed on a
per-converter basis. This register determines which
converter is being addressed for an Indexed command. It is
important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word
as detailed in Table 7. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
+Full Scale (0xFF)
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
This register value determines the ending address of the
burst data.
Determines which ADC is addressed. Valid states for this
register are 0x01 or 0x10. The two ADC cores cannot be
adjusted concurrently.
PARAMETER
Steps
TABLE 7. OFFSET ADJUSTMENTS
COARSE OFFSET
+133LSB (+47mV)
1.04LSB (0.37mV)
-133LSB (-47mV)
0.0LSB (0.0mV)
0x20[7:0]
255
20
0.04LSB (0.014mV)
+5LSB (+1.75mV)
-5LSB (-1.75mV)
FINE OFFSET
0x21[7:0]
0.0LSB
255
KAD5512P-50
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium and
fine steps. Coarse gain is a 4-bit adjustment while medium
and fine are 8-bit. Multiple Coarse Gain Bits can be set for a
total adjustment range of +/- 4.2%. ( ‘0011’ =~ -4.2% and
‘1100’ =~ +4.2% ) It is recommended to use one of the coarse
gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and
fine-tune the gain using the registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 16). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
+Full Scale (0xFF)
–Full Scale (0x00)
Nominal Step Size
Mid–Scale (0x80)
PARAMETER
0x22[3:0]
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
Steps
Bit3
Bit2
Bit1
Bit0
TABLE 8. COARSE GAIN ADJUSTMENT
VALUE
TABLE 10. POWER-DOWN CONTROL
000
001
010
100
MEDIUM GAIN
NOMINAL COARSE GAIN ADJUST
0x23[7:0]
0.016%
0.00%
+2%
256
-2%
POWER DOWN MODE
Normal Operation
+2.8
+1.4
-2.8
-1.4
(%)
Sleep Mode
Pin Control
Nap Mode
0x25[2:0]
FINE GAIN
0x24[7:0]
0.0016%
-0.20%
0.00%
+0.2%
January 16, 2009
256
FN6805.0