KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 22

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows
the allowable sample rate ranges for the slow and fast
settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
The procedure for setting output_mode_B is shown in
Figure 44. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
Device Test
The KAD5512-50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing. A
static word can be placed on the output bus, or two different
words can alternate. In the alternate mode, the values
defined as Word 1 and Word 2 (as shown in Table 16) are
set on the output bus on alternating clock phases. The test
mode is enabled asynchronously to the sample clock,
therefore several sample clock cycles may elapse before the
data is present on the output bus.
OUTPUT_MODE_B
CONFIG_STATUS
DLL RANGE
This bit sets the DLL operating range to fast (default) or
slow.
FIGURE 39. SETTING OUTPUT_MODE_B REGISTER
Slow
Fast
READ
READ
0x74
0x75
TABLE 15. DLL RANGES
DESIRED
VALUE
MIN
160
80
22
MAX
200
500
WRITE TO
MSPS
MSPS
UNIT
0x74
KAD5512P-50
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 17.
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
VALUE
0000
0001
0010
0011
0100
0101
0110
1000
0111
TABLE 16. OUTPUT TEST MODES
Negative Full-Scale
Positive Full-Scale
OUTPUT TEST
Checkerboard
User Pattern
0xC0[3:0]
Reserved
Reserved
One/Zero
Midscale
MODE
Off
user_patt1
WORD 1
0xAAAA
0xFFFF
0xFFFF
0x8000
0x0000
N/A
N/A
January 16, 2009
user_patt2
WORD 2
0x5555
0x0000
N/A
N/A
N/A
N/A
N/A
FN6805.0