KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 3

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Table of Contents
Absolute Maximum Ratings ......................................... 4
Thermal Information...................................................... 4
Electrical Specifications ............................................... 4
Digital Specifications .................................................... 6
Timing Diagrams ........................................................... 6
Switching Specifications .............................................. 7
Pinout/Package Information......................................... 8
Typical Performance Curves ........................................ 10
Theory of Operation ...................................................... 13
Pin Descriptions.......................................................... 8
Pin Configuration ........................................................ 9
Functional Description ................................................ 13
Power-On Calibration ................................................. 13
User Initiated Reset .................................................... 14
Analog Input ............................................................... 14
Clock Input ................................................................. 15
Jitter............................................................................ 16
Voltage Reference...................................................... 16
Digital Outputs ............................................................ 16
Over Range Indicator ................................................. 16
Power Dissipation....................................................... 16
Nap/Sleep................................................................... 16
Data Format ............................................................... 17
3
KAD5512P-50
Serial Peripheral Interface ........................................... 19
Equivalent Circuits ....................................................... 24
Layout Considerations................................................. 25
Definitions ..................................................................... 26
Revision History ........................................................... 26
Package Outline Drawing............................................. 27
L72.10x10D .................................................................... 27
SPI Physical Interface................................................ 19
SPI Configuration....................................................... 19
Device Information ..................................................... 20
Indexed Device Configuration/Control ....................... 20
Global Device Configuration/Control.......................... 21
Device Test ................................................................ 22
SPI Memory Map ....................................................... 23
Split Ground and Power Planes................................. 25
Clock Input Considerations ........................................ 25
Exposed Paddle......................................................... 25
Bypass and Filtering .................................................. 25
LVDS Outputs ............................................................ 25
LVCMOS Outputs ...................................................... 25
Unused Inputs............................................................ 25
January 16, 2009
FN6805.0