KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 12

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
List of Tables
Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 26
Table 2. Internal Function Block Status ........................................................................................................................ 29
Table 3. Port 5 PHY P5-MII/RMII Signals .................................................................................................................... 36
Table 4. Switch MAC5 MII Signals............................................................................................................................... 37
Table 5. Port 5 MAC5 SW5-RMII Connection.............................................................................................................. 39
Table 6. SNI Signals..................................................................................................................................................... 40
Table 7. Tail Tag Rules ................................................................................................................................................ 44
Table 8. FID+DA Look-Up in the VLAN Mode ............................................................................................................. 46
Table 9. FID+SA Look-Up in the VLAN Mode.............................................................................................................. 46
Table 10. SPI Connections .......................................................................................................................................... 49
Table 11. MII Management Interface Frame Format ................................................................................................... 51
Table 12. Serial Management Interface (SMI) Frame Format ..................................................................................... 51
Table 13. 100BT Rate Selection for the Rate limit....................................................................................................... 87
Table 14. 10BT Rate Selection for the Rate Limit........................................................................................................ 87
Table 15. Static MAC Address Table ........................................................................................................................... 89
Table 16. VLAN Table .................................................................................................................................................. 91
Table 17. VLAN ID and Indirect Registers ................................................................................................................... 92
Table 18. Dynamic MAC Address Table ...................................................................................................................... 93
Table 19. Port1 MIB Counter Indirect Memory Offerts................................................................................................. 94
Table 20. Format of “Per Port” MIB Counter................................................................................................................ 95
Table 21. All Port Dropped Packet MIB Counters........................................................................................................ 95
Table 22. Format of “All Dropped Packet” MIB Counter .............................................................................................. 95
Table 23. EEPROM Timing Parameters .................................................................................................................... 103
Table 24. SNI Timing Parameters.............................................................................................................................. 104
Table 25. MAC Mode MII Timing Parameters............................................................................................................ 105
Table 26. PHY Mode MII Timing Parameters ............................................................................................................ 106
Table 27. RMII Timing Parameters ............................................................................................................................ 107
Table 28. SPI Input Timing Parameters ..................................................................................................................... 108
Table 29. SPI Output Timing Parameters .................................................................................................................. 109
Table 30. Auto-Negotiation Timing Parameters......................................................................................................... 110
Table 31. MDC/MDIO Typical Timing Parameters..................................................................................................... 111
Table 32. Reset Timing Parameters .......................................................................................................................... 112
Table 33. Transformer Selection Criteria ................................................................................................................... 114
Table 34. Qualified Magnetic Vendors ....................................................................................................................... 114
Table 35. Typical Reference Crystal Characteristics ................................................................................................. 114
12
March 2012
M9999-032612-1.5