KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 37

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KSZ8895MQ_12

Manufacturer Part Number
KSZ8895MQ_12
Description
Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
Micrel, Inc.
Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ
Table 4 shows two connection manners:
Please see the pin [91,86,87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII
works with 25MHz clock for 100Base-TX, SW5-MII works with 2.5MHz clock for 10Base-T.
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MQ/RQ/FMQ. These interfaces are
nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has
indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a
signal that indicates a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER
is not provided on the SW-MII interface for MAC mode operation. Normally MRXER would indicate a receive error
coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals
are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing
with the KSZ8895MQ/RQ/FMQ has an MRXER pin, it should be tied low. For MAC mode operation with an external
PHY, if the device interfacing with the KSZ8895MQ/RQ/FMQ has an MTXER pin, it should be tied low.
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The
KSZ8895RQ supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the
device, and has the following key characteristics:
March 2012
External MAC
KSZ8895MQ/RQ/FMQ PHY Mode Connection
MRXDV
MRXER
MTXEN
MTXER
MRXD3
MRXD2
MRXD1
MRXD0
1. The first is an external MAC connects to SW5-MII PHY mode.
2. The second is an external PHY connects to SW5-MII MAC mode.
MTXD3
MTXD2
MTXD1
MTXD0
MCOL
MCRS
MRXC
MTXC
KSZ8895MQ/RQ/FMQ
SW5-MII Signals
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMTXEN
SMTXER
SMRXDV
Not used
SMRXC
SMTXC
SCOL
SCRS
Table 4. Switch MAC5 MII Signals
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Receive data valid
Collision detection
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
Transmit enable
Transmit clock
Transmit error
Receive clock
Carrier sense
Receive error
Description
37
KSZ8895MQ/RQ/FMQ MAC Mode Connection
External
MTXEN
MRXDV
MRXER
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MRXD3
MRXD2
MRXD1
MRXD0
MCOL
MCRS
MRXC
MTXC
PHY
KSZ8895MQ/RQ/FMQ
SW5-MII Signals
SMRXD[3]
SMRXD[2]
SMRXD[1]
SMRXD[0]
SMTXD[3]
SMTXD[2]
SMTXD[1]
SMTXD[0]
SMRXDV
SMTXEN
SMTXER
Not used
SMRXC
SMTXC
SCRS
SCOL
KSZ8895MQ/RQ/FMQ
M9999-032612-1.5
Not used
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input

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