KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 46

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
Advanced VLAN features are also supported in KSZ8895MQ/RQ/FMQ, such as “VLAN ingress filtering” and “discard
non PVID” defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis.
Rate Limiting Support
The KSZ8895MQ/RQ/FMQ provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate
limit is less than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate
for 100BT or 10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0-3
Ingress/Egress Limit Control section). The rate limit is independently on the “receive side” and on the “transmit side”
on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side,
the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the
transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate
Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte,
in addition to the data field (from packet DA to FCS).
Ingress Rate Limit
For ingress rate limiting, KSZ8895MQ/RQ/FMQ provides options to selectively choose frames from all types,
multicast, broadcast, and flooded unicast frames by bits [3-2] of the port rate limit control register. The
KSZ8895MQ/RQ/FMQ counts the data rate from those selected type of frames. Packets are dropped at the ingress
port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when
the ingress rate limit flow control is enabled by the port rate limit control register bit 4. The ingress rate limiting
supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by
bits[4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default
of the register 128 and 129. In the ingress rate limit, set register 135 global control 19 bit 3 to enable queue-based
rate limit if using two-queue or four-queue mode. All related ingress ports and egress port should be split to two-
queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use Q0-Q3 for
priority 0-3 by bit[6-0] of the port register ingress limit control 1-4. The two-queue mode will use Q0-Q1 for priority 0-
1by bit[6-0] of the port register ingress limit control 1-2. The priority levels in the packets of the 802.1p and DiffServ
can be programmed to priority 0-3 by the register 128 and 129 for a re-mapping.
March 2012
Static MAC table
Dynamic MAC table
DA found in
SA+FID found in
Yes
Yes
Yes
Yes
No
No
Yes
No
Do Not care
Do Not care
USE FID
Flag?
Action
The SA+FID will be learned into the dynamic table.
Time stamp will be updated.
0
1
1
1
Table 8. FID+DA Look-Up in the VLAN Mode
Table 9. FID+SA Look-Up in the VLAN Mode
FID Match?
Do Not care
Do Not care
Do Not care
Yes
No
No
Dynamic MAC table
DA+FID found in
Do Not care
Do Not care
Yes
Yes
No
No
46
Action
Broadcast to the membership ports defined in
the VLAN table bit[11:7].
Send to the destination port defined in the
dynamic MAC table bit[57:55].
Send to the destination port(s) defined in the
static MAC table bit[52:48].
Broadcast to the membership ports defined in
the VLAN table bit[11:7].
Send to the destination port defined in the
dynamic MAC table bit[57:55].
Send to the destination port(s) defined in the
static MAC table bit[52:48].
KSZ8895MQ/RQ/FMQ
M9999-032612-1.5