KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 77

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
Advanced Control Registers (Continued)
March 2012
Address
Register 134 (0x86): Global Control 18
7
6
5
4 – 0
Register 135 (0x87): Global Control 19
7
6
5 – 4
3
2
1 – 0
Register 144 (0x90): TOS Priority Control Register 0
The Ipv4/Ipv6 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to
determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64
possibilities, and the singular code that results is mapped to the value in the corresponding bit in the DSCP register.
7 – 6
5 – 4
3 – 2
Name
Reserved
Self Address Filter Enable
Unknown IP multicast packet
forward
Unknown IP multicast packet
forward port map
Reserved
Reserved
Ingress Rate Limit Period
Queue-based Egress Rate
Limit Enabled
Insertion Source Port PVID
Tag Selection Enable
Reserved
DSCP[7:6]
DSCP[5:4]
DSCP[3:2]
Description
N/A
1 = Enable filtering of self-address unicast and
multicast packet
0 = Do not filter self-address packet
Note: The self-address filtering will filter packets on
the egress port , self MAC address is assigned in
the register 104-109.
1 = enable supporting unknown IP multicast packet
forward
0 = disable
00000 = filter uknown IP multiicast packet
00001 = forward uknown IP multicast packet to port
1
00011 = forward uknown IP multicast packet to port
1, port 2
…
11111 = broadcast uknown IP multicast packet to
all ports
N/A Do not change.
N/A Do not change.
The unit period for calculating Ingress Rate Limit
00 = 16 ms
01 = 64 ms
1x = 256 ms
Enable Queue-based Egress Rate Limit
0 = port-base Egress Rate Limit (default)
1 = queue-based Egress Rate Limit
1 = enable source port PVID tag insertion or non-
insertion option on the egress port for each source
port PVID based on the ports registers control 8.
0 = disable, all packets from any ingress port will be
inserted PVID based on port register control 0 bit 2.
N/A Do not change
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x03
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x02
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x01
77
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KSZ8895MQ/RQ/FMQ
RO
RO
RO
RO
M9999-032612-1.5
Default
00000
01
00
00
00
00
0
0
0
0
0
0
0