KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 62

no-image

KSZ8895MQ_12

Manufacturer Part Number
KSZ8895MQ_12
Description
Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
Micrel, Inc.
Global Registers (Continued)
March 2012
Address
Register 12 (0x0C): Global Control 10
7
6
5 – 4
3
2
1
0
Register 13 (0x0D): Global Control 11
7 – 0
Register 14 (0x0E): Power Down Management Control 1
7
6
Name
Reserved
Satus of device with RMII
interface at clock mode or
normal mode, default is
clock mode with 25MHz
Crystal clock from pins
X1/X2
(used for RMII of the
KSZ8895RQ only)
CPU interface clock select
Reserved
Enable restore preamble
Tail Tag Enable
Pass Flow Control Packet
Factory Testing
Reserved
Reserved
Description
Reserved
1 = The device is in clock mode when use RMII
interface, 25 MHz Crystal clock input as clock source
for internal PLL. This internal PLL will provide the 50
MHz output on the pin SMRXC for RMII reference
clock (Default).
0 = The device is in normal mode when use SW4-RMII
interface and 50 MHz clock input from external clock
through pin SM4TXC as device’s clock source and
internal PLL clock source from this pin not from the
25MHz crystal.
Note: This bit is set by strap option only. Write to this
bit has no effect on mode selection.
Note: The normal mode is used in SW5-RMII interface
reference clock from external.
Select the internal clock speed for SPI, MDI interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
10 = 125MHz (for hign speed SPI about 25MHz)
11 = Reserved
N/A Do not change.
This bit is to enable PHY5, when in 10BT mode, to
restore preamble before sending data on P5-MII
interface.
1 = Enable PHY5 to restore preamble.
0 = Disable PHY5 to restore preamble.
Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of data right before FCS.
0 = Do not insert.
1 = Switch will not filter 802.1x “flow control” packets.
0 = Switch will filter 802.1x “flow control” packets.
N/A Do not change.
N/A Do not change.
N/A Do not change.
62
Mode
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
KSZ8895MQ/RQ/FMQ
Pin LED[2][2]
strap option.
PD(0): Select
SW5-RMII at
normal mode to
receive external
50MHz RMII
reference clock
PU(1): (default)
Select SW5-
RMII at clock
mode, RMII
output 50MHz
Note: LED[2][2]
has internal pull-
up.
M9999-032612-1.5
00000000
Default
01
0
1
0
1
0
0
0
0

Related parts for KSZ8895MQ_12