KSZ8895MQ_12 MICREL [Micrel Semiconductor], KSZ8895MQ_12 Datasheet - Page 41

• Manufacturer Part Number: KSZ8895MQ_12
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Advanced Functionality
QoS Priority Support
The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications such as VoIP and video conferencing.
The KSZ8895MQ/RQ/FMQ offers one, two, or four priority queues per port by setting the port registers xxx control 9
bit 1 and the port registers xxx control 0 bit 0, the 1/2/4 queues split as follows,
[Port registers xxx control 9 bit 1, control 0 bit 0] = 00 single output queue as default.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 01 egress port can be split into two priority transmit queues.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 10 egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8895MQ/RQ/FMQ. The queue 3 is the highest priority
queue and queue 0 is the lowest priority queue. The port registers xxx control 9 bit 1 and the port registers xxx
control 0 bit 0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit
queue is not split, high priority and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fair
queuing for the four priority queue scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by
their bit[6:0].
Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the
2-bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4
Queues) into two-queue mode with priority high or low.
Please see the descriptions of the register 130 bits [7:6] for detail.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets
received at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if
the corresponding transmit queue is split. The Port Registers Control 0 Bits[4:3] is used to enable port-based priority
for ports 1, 2, 3, 4 and 5, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8895MQ/RQ/FMQ examines the ingress (incoming) packets to determine whether
they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority
mapping” value, as specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7
value to 2-bit result of 0-3 priority levels. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit[5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
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March 2012
M9999-032612-1.5