PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 116
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PIC17C752
Manufacturer Part Number
PIC17C752
Description
High-Performance 8-Bit CMOS EPROM Microcontrollers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC17C752.pdf
(320 pages)
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Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
FIGURE 14-8: ASYNCHRONOUS RECEPTION
TABLE 14-7:
DS30264A-page 116
Address
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
Rcv buffer reg
(interrupt flag)
(RX/DT pin)
Read Rcv
buffer reg
OERR bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
Rcv shift
RCREG
reception.
reg
CREN
RCIF
Name
PIR1
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
RX
causing the OERR (overrun) bit to be set.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
Baud rate generator register
Baud rate generator register
SSPIE
CSRC
SSPIF
CSRC
SPEN
SPEN
RBIF
RBIE
Bit 7
RX7
RX7
bit0
TMR3IF TMR2IF TMR1IF
TMR3IE TMR2IE TMR1IE
BCLIE
BCLIF
bit1
Bit 6
RX9
RX6
TX9
RX9
RX6
TX9
SREN
SREN
TXEN
TXEN
ADIE
Bit 5
ADIF
RX5
RX5
bit7/8
CREN
SYNC
CREN
SYNC
Bit 4
RX4
RX4
Preliminary
Stop
—
—
bit
Word 1
RCREG
Start
CA2IF
CA2IE
CA4IF
CA4IE
bit
Bit 3
RX3
RX3
—
—
—
—
bit0
7.
8.
9.
CA1IE
CA3IE
CA1IF
FERR
CA3IF
FERR
Note:
Bit 2
RX2
RX2
—
—
Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
Read RCREG for the 8-bit received data.
If an overrun error occurred, clear the error by
clearing the OERR bit.
bit7/8
TX1IE
OERR
TRMT
TX2IE
OERR
TRMT
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
TX1IF
TX2IF
Bit 1
RX1
RX1
Stop
bit
Word 2
RCREG
RC1IF
RC1IE
RC2IF
RC2IE
RX9D
RX9D
TX9D
TX9D
Bit 0
RX0
RX0
Start
bit
1997 Microchip Technology Inc.
0000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
Value on
POR,
BOR
bit7/8
Stop
Word 3
bit
other resets
Value on all
0000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
(Note1)
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