PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 23

• Manufacturer Part Number: PIC17C752
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 5-1:
TABLE 5-2:
TABLE 5-3:
5.1.4
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
Note 1: When BOR is enabled, else the BOR status bit is unknown
Power-on Reset
Brown-out Reset
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
1997 Microchip Technology Inc.
POR
0
1
1
1
1
1
0
0
x
Configuration
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
4: When BOR is enabled, else the BOR status bit is unknown.
Oscillator
EC, RC
XT, LF
TIME-OUT SEQUENCE
then executed.
mid-range devices.
BOR
0
1
1
1
1
0
0
0
x
(1)
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
TO
1
1
0
0
1
x
0
x
1
Greater of: 96 ms or 1024T
Greater of: 96 ms or 1024T
(3)
GLINTD is set
GLINTD is clear
PD
1
0
1
0
1
x
x
0
1
Power-up
Power-on Reset
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
MCLR Reset during normal operation
Brown-out Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
CLRWDT instruction executed
Preliminary
OSC
OSC
PCH:PCL
PC + 1
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/V
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization condi-
tions for all the registers.
(1)
Wake up from
1024T
SLEEP
Event
—
--11 1100
--11 1101
--11 1111
--11 1011
--11 0111
--11 0011
--11 1011
--10 1011
OSC
CPUSTA
(4)
MCLR Reset
—
—
DS30264A-page 23
OST Active
PP
Yes
Yes
Yes
Yes
Yes
No
No
No
pin must be
(2)
(2)
(2)
(2)
BOR
—
—