PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 39

• Manufacturer Part Number: PIC17C752
• Description: High-Performance 8-Bit CMOS EPROM Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

7.0
There are two memory blocks in the PIC17C75X; pro-
gram memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
The data memory can further be broken down into
General Purpose RAM and the Special Function Reg-
isters (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to con-
trol the peripheral modules are described in the section
discussing each individual peripheral module.
7.1
PIC17C75X devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The reset vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 7-1).
7.1.1
The PIC17C75X can operate in one of four possible
program memory configurations. The configuration is
selected by configuration bits. The possible modes
are:
• Microprocessor
• Microcontroller
• Extended Microcontroller
• Protected Microcontroller
The microcontroller and protected microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data.
The protected microcontroller mode also enables the
code protection feature.
The extended microcontroller mode accesses both the
internal program memory as well as external program
memory. Execution automatically switches between
internal and external memory. The 16-bits of address
allow a program memory range of 64K-words.
The microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program mem-
ory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
The different modes allow different access to the con-
figuration bits, test memory, and boot ROM. Table 7-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
1997 Microchip Technology Inc.
MEMORY ORGANIZATION
Program Memory Organization
PROGRAM MEMORY OPERATION
Preliminary
FIGURE 7-1:
Note 1:
CALL, RETURN
RETFIE, RETLW
User memory space may be internal, external, or
both. The memory configuration depends on the
processor mode.
T0CKI Pin Interrupt Vector
Peripheral Interrupt Vector
INT Pin Interrupt Vector
Timer0 Interrupt Vector
PROGRAM MEMORY MAP
AND STACK
Stack Level 16
Stack Level 1
Reset Vector
Test EPROM
PC<15:0>
Boot ROM
WDTPS0
WDTPS1
Reserved
Reserved
Reserved
BODEN
FOSC0
FOSC1
PM0
PM1
PM2
16
DS30264A-page 39
FDFFh
FE00h
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE08h
FE0Dh
FE0Eh
FE0Fh
FE10h
FF5Fh
FF60h
FFFFh
0000h
0008h
0010h
0018h
0020h
0021h
1FFFh
(PIC17C752)
3FFFh
(PIC17C756)