PIC17C752 MICROCHIP [Microchip Technology], PIC17C752 Datasheet - Page 157
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PIC17C752
Manufacturer Part Number
PIC17C752
Description
High-Performance 8-Bit CMOS EPROM Microcontrollers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC17C752.pdf
(320 pages)
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15.2.12 STOP CONDITION TIMING
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator
times out, the SCL pin will be brought high, and one
T
SDA pin will be de-asserted. When the SDA pin is
sampled high while SCL is high, the PEN bit will be
automatically cleared, and the P bit (SSPSTAT<4>) is
set which in turn will set the SSPIF flag. (Figure 15-34)
FIGURE 15-34: STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
1997 Microchip Technology Inc.
(baud rate generator rollover count) later, the
SCL
SDA
Write to SSPCON2
Falling edge of
9th clock
Note: T
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup stop condition.
T
T
BRG
BRG
T
SCL brought high after T
BRG
Preliminary
P
T
SCL = 1 for T
after SDA sampled high, PEN bit (SSPCON2<2>) is
automatically cleared. P bit (SSPSTAT<4>) is set
BRG
Whenever the CPU decides to take control of the bus,
it will first determine if the bus is busy by checking the
S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
15.2.12.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
BRG
BRG
, followed by SDA = 1 for T
BRG
DS30264A-page 157
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